Texas Instruments TMS320C6747 DSP manual HC Current Control Register Hccontrolcurrented, Cced

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Registers

3.10 HC Current Control Register (HCCONTROLCURRENTED)

The HC current control register (HCCONTROLCURRENTED) defines the physical address of the next endpoint descriptor (ED) on the control ED list. HCCONTROLCURRENTED is shown in Figure 11 and described in Table 11.

Figure 11. HC Current Control Register (HCCONTROLCURRENTED)

31			16
	CCED
	R/W-0
15	4	3	0
CCED			Reserved
R/W-0			R-0

LEGEND: R/W = Read/Write; R = Read only; -n= value after reset

Table 11. HC Current Control Register (HCCONTROLCURRENTED) Field Descriptions

Bit	Field	Value	Description
31-4	CCED	0-FFF FFFFh	Physical address of the current ED on the control ED list. This field represents bits 31-4 of the
			physical address of the next ED on the control ED list. EDs are assumed to begin on a 16-byte
			aligned address, so bits 3-0 of this pointer are assumed to be 0. For the restrictions on physical
			addresses, see Section 2.7.
			A value of 0 indicates that the USB host controller has reached the end of the control ED list
			without finding any transfers to process. This register is automatically updated by the USB host
			controller.
3-0	Reserved	0	Reserved

SPRUFM8–September 2008	Universal Serial Bus OHCI Host Controller	21
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Contents Literature Number SPRUFM8 September Users GuideSPRUFM8-September Contents List of Figures List of Tables Read This First Purpose of the Peripheral Universal Serial Bus Ohci Host Controller2 USB1 Module Local Bus Clock and Local Reset USB1 Module Clock and ResetInternal System Bus Clocks Needed by the USB1 Module 3 USB1 Module Bus 48-MHz Reference ClockUSB1 Module Open Host Controller Interface Functionality USB1 Module Differences From Ohci Specification for USBOhci USB Suspend State Implementation of Ohci Specification for USBOhci Interrupts USB Host Controller Access to System MemoryPhysical Addressing MMUUSB Host Controller Registers Ohci Revision Number Register Hcrevision HC Operating Mode Register HccontrolOhci Revision Number Register Hcrevision Field Descriptions REVPeriodic list enable Control list enableControl ED per bulk ED Control EDs per bulk EDSOC HC Command and Status Register HccommandstatusOCR BLF CLF HCR OCRHC Interrupt and Status Register Hcinterruptstatus Rhsc FNO WDHRhsc MIE HC Interrupt Enable Register HcinterruptenableHC Interrupt Disable Register Hcinterruptdisable HC Current Periodic Register Hcperiodcurrented HC Hcaa Address Register HchccaHC Hcaa Address Register Hchcca Field Descriptions HccaHC Head Control Register Hccontrolheaded HC Head Control Register Hccontrolheaded Field DescriptionsChed HC Current Control Register Hccontrolcurrented CcedController HC Current Bulk Register Hcbulkcurrented HC Head Bulk Register HcbulkheadedHC Head Bulk Register Hcbulkheaded Field Descriptions HC Current Bulk Register Hcbulkcurrented Field DescriptionsHC Frame Interval Register Hcfminterval HC Head Done Register HcdoneheadHC Head Done Register Hcdonehead Field Descriptions HC Frame Interval Register Hcfminterval Field DescriptionsHC Frame Number Register Hcfmnumber HC Frame Remaining Register HcfmremainingHC Frame Number Register Hcfmnumber Field Descriptions FRTHC Periodic Start Register Hcperiodicstart HC Periodic Start Register HcperiodicstartLST HC Low-Speed Threshold Register Hclsthreshold628h Reserved 13-0HC Root Hub a Register Hcrhdescriptora Field Descriptions HC Root Hub a Register HcrhdescriptoraPotpg Nocp Ocpm NPS PSM NDPHC Root Hub B Register Hcrhdescriptorb Field Descriptions HC Root Hub B Register HcrhdescriptorbPPCM3 PPCM2 PPCM1 PPCM0 PPCM3HC Root Hub Status Register Hcrhstatus Field Descriptions HC Root Hub Status Register HcrhstatusHC Port 1 Status and Control Register HCRHPORTSTATUS1 PRS/SPR Effect Port 2 current connect status has not changed HC Port 2 Status and Control Register HCRHPORTSTATUS2Begin signaling USB reset to port When read as 0, USB reset is not being sent to portEnd of the USB reset sequence Write of 1 to this bit clears the port 2 port enable bitRfid DSP