Texas Instruments TMS320C6747 DSP manual Prs/Spr

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Table 23. HC Port 1 Status and Control Register (HCRHPORTSTATUS1) Field Descriptions (continued)

Bit

Field

Value

Description

8

PPS/SPP

 

Port 1 port power status/set port power. The host controller driver can write a 1 to this bit to set the

 

 

 

port 1 port power status bit; a write of 0 has no effect. The device does not provide signals from the

 

 

 

USB host controller to control external port power, so if required, USB host port power control

 

 

 

signals must be controlled through other means. Software can track the current power state using

 

 

 

the port power status bit and other power control bits, but those bits have no direct effect on

 

 

 

external port power control. This bit has no relationship to the OTG controller register bits that relate

 

 

 

to VBUS. System software can update this register to simplify host controller driver and/or OTG

 

 

 

driver coding.

 

 

0

Port 1 power is disabled.

 

 

1

Port 1 power is enabled.

7-5

Reserved

0

Reserved

4

PRS/SPR

 

Port 1 port reset status/set port reset. A write of 1 to this bit sets the port 1 port reset status bit and

 

 

 

causes the USB host controller to begin signaling USB reset to port 1; a write of 0 has no effect.

 

 

0

USB reset is not being sent to port 1.

 

 

1

Port 1 is signaling the USB reset.

3

POCI/CSS

 

Port 1 port overcurrent indicator/clear suspend status. A write of 1 to this bit when port 1 port

 

 

 

suspend status is 1 causes resume signaling on port 1; a write of 1 when port 1 port suspend

 

 

 

status is 0 has no effect; a write of 0 has no effect. The device does not provide inputs for signaling

 

 

 

external overcurrent indication to the USB host controller. Overcurrent monitoring, if required, must

 

 

 

be handled through some other mechanism.

 

 

0

Port 1 port overcurrent condition has not occurred.

 

 

1

Port 1 port overcurrent condition has occurred.

2

PSS/SPS

 

Port 1 port suspend status/set port suspend. A write of 1 to this bit when port 1 current connect

 

 

 

status is 1 sets the port 1 port suspend status bit and places port 1 in USB suspend state; a write of

 

 

 

1 when port 1 current connect status is 0 sets the connect status change to inform the USB host

 

 

 

controller driver software of an attempt to suspend a disconnected device; a write of 0 has no

 

 

 

effect. This bit is cleared automatically at the end of the USB resume sequence and also at the end

 

 

 

of the USB reset sequence.

 

 

0

Port 1 is not in the USB suspend state.

 

 

1

Port 1 is in the USB suspend state or is in the resume sequence.

1

PES/SPE

 

Port 1 port enable status/set port enable. A write of 1 to this bit when port 1 current connect status

 

 

 

is 1 sets the port 1 port enable status bit; a write of 1 when port 1 current connect status is 0 has no

 

 

 

effect; a write of 0 has no effect. This bit is automatically set at completion of port 1 USB reset, if it

 

 

 

was not already set before the USB reset completed; and this bit is automatically set at the end of a

 

 

 

USB suspend, if the port was not enabled when the USB resume completed.

 

 

0

Port 1 is disabled.

 

 

1

Port 1 is enabled.

0

CCS/CPE

 

Port 1 current connection status/clear port enable. If the DR[1] bit in the HC root hub B register

 

 

 

(HCRHDESCRIPTORB) is set to 1 to indicate a nonremovable USB device on port 1, this bit is set

 

 

 

after a root hub reset to inform the system that the device is attached. A write of 1 clears this bit; a

 

 

 

write of 0 has no effect.

 

 

0

No USB device is attached to port 1.

 

 

1

USB device is attached to port 1.

SPRUFM8–September 2008

Universal Serial Bus OHCI Host Controller

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Contents Literature Number SPRUFM8 September Users GuideSPRUFM8-September Contents List of Figures List of Tables Read This First Purpose of the Peripheral Universal Serial Bus Ohci Host Controller3 USB1 Module Bus 48-MHz Reference Clock USB1 Module Clock and Reset2 USB1 Module Local Bus Clock and Local Reset Internal System Bus Clocks Needed by the USB1 ModuleUSB1 Module Open Host Controller Interface Functionality USB1 Module Differences From Ohci Specification for USBOhci USB Suspend State Implementation of Ohci Specification for USBMMU USB Host Controller Access to System MemoryOhci Interrupts Physical AddressingUSB Host Controller Registers REV HC Operating Mode Register HccontrolOhci Revision Number Register Hcrevision Ohci Revision Number Register Hcrevision Field DescriptionsControl EDs per bulk ED Control list enablePeriodic list enable Control ED per bulk EDOCR HC Command and Status Register HccommandstatusSOC OCR BLF CLF HCRRhsc FNO WDH HC Interrupt and Status Register HcinterruptstatusRhsc MIE HC Interrupt Enable Register HcinterruptenableHC Interrupt Disable Register Hcinterruptdisable Hcca HC Hcaa Address Register HchccaHC Current Periodic Register Hcperiodcurrented HC Hcaa Address Register Hchcca Field DescriptionsHC Head Control Register Hccontrolheaded Field Descriptions HC Head Control Register HccontrolheadedChed Cced HC Current Control Register HccontrolcurrentedController HC Current Bulk Register Hcbulkcurrented Field Descriptions HC Head Bulk Register HcbulkheadedHC Current Bulk Register Hcbulkcurrented HC Head Bulk Register Hcbulkheaded Field DescriptionsHC Frame Interval Register Hcfminterval Field Descriptions HC Head Done Register HcdoneheadHC Frame Interval Register Hcfminterval HC Head Done Register Hcdonehead Field DescriptionsFRT HC Frame Remaining Register HcfmremainingHC Frame Number Register Hcfmnumber HC Frame Number Register Hcfmnumber Field DescriptionsHC Periodic Start Register Hcperiodicstart HC Periodic Start Register HcperiodicstartReserved 13-0 HC Low-Speed Threshold Register HclsthresholdLST 628hNocp Ocpm NPS PSM NDP HC Root Hub a Register HcrhdescriptoraHC Root Hub a Register Hcrhdescriptora Field Descriptions PotpgPPCM3 HC Root Hub B Register HcrhdescriptorbHC Root Hub B Register Hcrhdescriptorb Field Descriptions PPCM3 PPCM2 PPCM1 PPCM0HC Root Hub Status Register Hcrhstatus Field Descriptions HC Root Hub Status Register HcrhstatusHC Port 1 Status and Control Register HCRHPORTSTATUS1 PRS/SPR Effect Port 2 current connect status has not changed HC Port 2 Status and Control Register HCRHPORTSTATUS2Write of 1 to this bit clears the port 2 port enable bit When read as 0, USB reset is not being sent to portBegin signaling USB reset to port End of the USB reset sequenceRfid DSP
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