Texas Instruments TMS320C6747 DSP manual HC Command and Status Register Hccommandstatus, Soc, Ocr

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Registers

3.3HC Command and Status Register (HCCOMMANDSTATUS)

The HC command and status register (HCCOMMANDSTATUS) shows the current state of the host controller and accepts commands from the host controller driver. HCCOMMANDSTATUS is shown in Figure 4 and described in Table 4.

Figure 4. HC Command and Status Register (HCCOMMANDSTATUS)

31

 

 

18

17

16

Reserved

 

 

 

SOC

R-0

 

 

 

R-0

15

4

3

2

1

0

Reserved

 

OCR

BLF

CLF

HCR

R-0

 

R/W-0

R/W-0

R/W-0

R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n= value after reset

Table 4. HC Command and Status Register (HCCOMMANDSTATUS) Field Descriptions

Bit

Field

Value

Description

31-18

Reserved

0

Reserved

17-16

SOC

0-3h

Scheduling overrun count. Counts the number of times a scheduling overrun occurs. This count is

 

 

 

incremented even if the host controller driver has not acknowledged any previous pending scheduling

 

 

 

overrun interrupt.

15-4

Reserved

0

Reserved

3

OCR

0-1

Ownership change request. The host controller driver sets this bit to gain ownership of the host

 

 

 

controller. The processor does not support SMI interrupts, so no ownership change interrupt occurs.

2

BLF

0-1

Bulk list filled. The host controller driver must set this bit if it modifies the bulk list to include new TDs. If

 

 

 

the HC current bulk register (HCBULKCURRENTED) is 0, the USB host controller does not begin

 

 

 

processing bulk list EDs unless this bit is set. When the USB host controller sees this bit set and begins

 

 

 

processing the bulk list, it clears this bit to 0.

1

CLF

0-1

Control list filled. The host controller driver must set this bit if it modifies the control list to include new

 

 

 

TDs. If the HC head control register (HCCONTROLHEADED) is 0, the USB host controller does not

 

 

 

begin processing control list EDs unless this bit is set. When the USB host controller sees this bit set

 

 

 

and begins processing the control list, it clears this bit to 0.

0

HCR

 

Host controller reset.

 

 

0

No effect.

1Initiates a software reset of the USB host controller. This transitions the USB host controller to the USB suspend state. This resets most USB host controller OHCI registers. OHCI register accesses must not be attempted until a read of this bit returns a 0. A write of 1 to this bit does not reset the root hub and does not signal USB reset to downstream USB functions.

SPRUFM8–September 2008

Universal Serial Bus OHCI Host Controller

15

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Contents Literature Number SPRUFM8 September Users GuideSPRUFM8-September Contents List of Figures List of Tables Read This First Purpose of the Peripheral Universal Serial Bus Ohci Host Controller3 USB1 Module Bus 48-MHz Reference Clock USB1 Module Clock and Reset2 USB1 Module Local Bus Clock and Local Reset Internal System Bus Clocks Needed by the USB1 ModuleUSB1 Module Open Host Controller Interface Functionality USB1 Module Differences From Ohci Specification for USBOhci USB Suspend State Implementation of Ohci Specification for USBMMU USB Host Controller Access to System MemoryOhci Interrupts Physical AddressingUSB Host Controller Registers REV HC Operating Mode Register HccontrolOhci Revision Number Register Hcrevision Ohci Revision Number Register Hcrevision Field DescriptionsControl EDs per bulk ED Control list enablePeriodic list enable Control ED per bulk EDOCR HC Command and Status Register HccommandstatusSOC OCR BLF CLF HCRHC Interrupt and Status Register Hcinterruptstatus Rhsc FNO WDHRhsc MIE HC Interrupt Enable Register HcinterruptenableHC Interrupt Disable Register Hcinterruptdisable Hcca HC Hcaa Address Register HchccaHC Current Periodic Register Hcperiodcurrented HC Hcaa Address Register Hchcca Field DescriptionsHC Head Control Register Hccontrolheaded HC Head Control Register Hccontrolheaded Field DescriptionsChed HC Current Control Register Hccontrolcurrented CcedController HC Current Bulk Register Hcbulkcurrented Field Descriptions HC Head Bulk Register HcbulkheadedHC Current Bulk Register Hcbulkcurrented HC Head Bulk Register Hcbulkheaded Field DescriptionsHC Frame Interval Register Hcfminterval Field Descriptions HC Head Done Register HcdoneheadHC Frame Interval Register Hcfminterval HC Head Done Register Hcdonehead Field DescriptionsFRT HC Frame Remaining Register HcfmremainingHC Frame Number Register Hcfmnumber HC Frame Number Register Hcfmnumber Field DescriptionsHC Periodic Start Register Hcperiodicstart HC Periodic Start Register HcperiodicstartReserved 13-0 HC Low-Speed Threshold Register HclsthresholdLST 628hNocp Ocpm NPS PSM NDP HC Root Hub a Register HcrhdescriptoraHC Root Hub a Register Hcrhdescriptora Field Descriptions PotpgPPCM3 HC Root Hub B Register HcrhdescriptorbHC Root Hub B Register Hcrhdescriptorb Field Descriptions PPCM3 PPCM2 PPCM1 PPCM0HC Root Hub Status Register Hcrhstatus Field Descriptions HC Root Hub Status Register HcrhstatusHC Port 1 Status and Control Register HCRHPORTSTATUS1 PRS/SPR Effect Port 2 current connect status has not changed HC Port 2 Status and Control Register HCRHPORTSTATUS2Write of 1 to this bit clears the port 2 port enable bit When read as 0, USB reset is not being sent to portBegin signaling USB reset to port End of the USB reset sequenceRfid DSP
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