Texas Instruments TMS320C6747 DSP manual HC Root Hub Status Register Hcrhstatus

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Registers

3.21 HC Root Hub Status Register (HCRHSTATUS)

The HC root hub status register (HCRHSTATUS) reports the USB host controller root hub status. HCRHSTATUS is shown in Figure 22 and described in Table 22.

Figure 22. HC Root Hub Status Register (HCRHSTATUS)

31	30		18	17	16
CRWE			Reserved	OCIC	LPSC
R/W-0			R-0	R/W-0	R/W-0
15	14		2	1	0
DRWE			Reserved	OCI	LPS
R/W-0			R-0	R-0	R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n= value after reset
		Table 22. HC Root Hub Status Register (HCRHSTATUS) Field Descriptions
Bit	Field	Value	Description
31	CRWE		Clear remote wake-up enable.
		0	No effect..
		1	Clears the device remote wake-up enable bit.
30-18	Reserved	0	Reserved
17	OCIC		Overcurrent indication change. This bit is automatically set when the overcurrent indicator bit changes.
			This bit has no relationship to the OTG controller register bits that relate to VBUS. System software can
			update this register to simplify host controller driver and/or OTG driver coding.
		0	No effect.
		1	Clears this bit.
16	LPSC	0	Local power status change. Because the root hub does not support the local power status feature, this
			bit defaults to 0 and has no effect. This bit has no relationship to the OTG controller register bits that
			relate to VBUS. System software can update this register to simplify host controller driver and/or OTG
			driver coding.
15	DRWE		Device remote wake-up enable.
			When 1, this bit enables a connect status change event to be treated as a resume event, which causes
			a transition from USB suspend to USB resume state and sets the resume detected interrupt status bit.
			When 0, connect status change events do not cause a transition from USB suspend to USB resume
			state and the resume detected interrupt is not changed.
		0	A write of 0 has no effect.
		1	A write of 1 sets the device remote wake-up enable bit.
14-2	Reserved	0	Reserved
1	OCI	0	Overcurrent indicator. Because the device does not provide signals for external hardware to report
			overcurrent status to the USB host controller, this bit is always 0. This bit has no relationship to the
			OTG controller register bits that relate to VBUS.
0	LPS	0	Local power status. Because the root hub does not support the local power status feature, this bit
			defaults to 0 and has no effect. This bit has no relationship to the OTG controller register bits that relate
			to VBUS. System software can update this register to simplify host controller driver and/or OTG driver
			coding.

SPRUFM8–September 2008	Universal Serial Bus OHCI Host Controller	29
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Contents Literature Number SPRUFM8 September Users GuideSPRUFM8-September Contents List of Figures List of Tables Read This First Purpose of the Peripheral Universal Serial Bus Ohci Host Controller2 USB1 Module Local Bus Clock and Local Reset USB1 Module Clock and ResetInternal System Bus Clocks Needed by the USB1 Module 3 USB1 Module Bus 48-MHz Reference ClockUSB1 Module Open Host Controller Interface Functionality USB1 Module Differences From Ohci Specification for USBOhci USB Suspend State Implementation of Ohci Specification for USBOhci Interrupts USB Host Controller Access to System MemoryPhysical Addressing MMUUSB Host Controller Registers Ohci Revision Number Register Hcrevision HC Operating Mode Register HccontrolOhci Revision Number Register Hcrevision Field Descriptions REVPeriodic list enable Control list enableControl ED per bulk ED Control EDs per bulk EDSOC HC Command and Status Register HccommandstatusOCR BLF CLF HCR OCRRhsc HC Interrupt and Status Register HcinterruptstatusRhsc FNO WDH MIE HC Interrupt Enable Register HcinterruptenableHC Interrupt Disable Register Hcinterruptdisable HC Current Periodic Register Hcperiodcurrented HC Hcaa Address Register HchccaHC Hcaa Address Register Hchcca Field Descriptions HccaChed HC Head Control Register HccontrolheadedHC Head Control Register Hccontrolheaded Field Descriptions Controller HC Current Control Register HccontrolcurrentedCced HC Current Bulk Register Hcbulkcurrented HC Head Bulk Register HcbulkheadedHC Head Bulk Register Hcbulkheaded Field Descriptions HC Current Bulk Register Hcbulkcurrented Field DescriptionsHC Frame Interval Register Hcfminterval HC Head Done Register HcdoneheadHC Head Done Register Hcdonehead Field Descriptions HC Frame Interval Register Hcfminterval Field DescriptionsHC Frame Number Register Hcfmnumber HC Frame Remaining Register HcfmremainingHC Frame Number Register Hcfmnumber Field Descriptions FRTHC Periodic Start Register Hcperiodicstart HC Periodic Start Register HcperiodicstartLST HC Low-Speed Threshold Register Hclsthreshold628h Reserved 13-0HC Root Hub a Register Hcrhdescriptora Field Descriptions HC Root Hub a Register HcrhdescriptoraPotpg Nocp Ocpm NPS PSM NDPHC Root Hub B Register Hcrhdescriptorb Field Descriptions HC Root Hub B Register HcrhdescriptorbPPCM3 PPCM2 PPCM1 PPCM0 PPCM3HC Root Hub Status Register Hcrhstatus Field Descriptions HC Root Hub Status Register HcrhstatusHC Port 1 Status and Control Register HCRHPORTSTATUS1 PRS/SPR Effect Port 2 current connect status has not changed HC Port 2 Status and Control Register HCRHPORTSTATUS2Begin signaling USB reset to port When read as 0, USB reset is not being sent to portEnd of the USB reset sequence Write of 1 to this bit clears the port 2 port enable bitRfid DSP