Texas Instruments TMS320C6747 DSP HC Root Hub B Register Hcrhdescriptorb, PPCM3 PPCM2 PPCM1 PPCM0

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Registers

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3.20 HC Root Hub B Register (HCRHDESCRIPTORB)

The HC root hub B register (HCRHDESCRIPTORB) defines several aspects of the USB host controller root hub functionality. HCRHDESCRIPTORB is shown in Figure 21 and described in Table 21.

Note: The device does not provide connections from the USB host controller to pins to provide external port power switching. Systems that implement port power switching must use other mechanisms to control port power.

Figure 21. HC Root Hub B Register (HCRHDESCRIPTORB)

31

20

19

18

17

16

PPCM[15-4]

 

PPCM[3]

PPCM[2]

PPCM[1]

PPCM[0]

R/W-0

 

R/W-0

R/W-0

R/W-0

R/W-0

15

4

3

2

1

0

DR[15-4]

 

DR[3]

DR[2]

DR[1]

DR[0]

R/W-0

 

R/W-0

R/W-0

R/W-0

R/W-0

LEGEND: R/W = Read/Write; -n= value after reset

Table 21. HC Root Hub B Register (HCRHDESCRIPTORB) Field Descriptions

Bit

Field

Value

Description

 

31-20

PPCM[15-4]

0

Port power control mask. PPCM[15] through PPCM[4] are reserved.

 

19

PPCM[3]

 

Port power control mask. PPCM[3] is the port power control mask for downstream port 3. Defines

 

 

 

whether downstream port 3 has port power controlled by the global power control. System software can

 

 

 

update these bits to simplify host controller driver and/or OTG driver coding.

 

 

0

Global power control is implemented for downstream port 3.

 

 

 

1

Per-port power control is implemented for downstream port 3.

 

18

PPCM[2]

 

Port power control mask. PPCM[2] is the port power control mask for downstream port 2. Defines

 

 

 

whether downstream port 2 has port power controlled by the global power control. System software can

 

 

 

update these bits to simplify host controller driver and/or OTG driver coding.

 

 

0

Global power control is implemented for downstream port 2.

 

 

 

1

Per-port power control is implemented for downstream port 2.

 

17

PPCM[1]

 

Port power control mask. PPCM[1] is the port power control mask for downstream port 1. Defines

 

 

 

whether downstream port 1 has port power controlled by the global power control. System software can

 

 

 

update these bits to simplify host controller driver and/or OTG driver coding.

 

 

0

Global power control is implemented for downstream port 1.

 

 

 

1

Per-port power control is implemented for downstream port 1.

 

16

PPCM[0]

0

Port power control mask. PPCM[0] is reserved.

 

15-4

DR[15-4]

0

Device removable. DR[15] through DR[4] are reserved.

 

3

DR[3]

 

Device removable. DR[3] is the device removable bit for downstream port 3. Defines whether

 

 

 

downstream port 3 has a removable or nonremovable device.

 

 

 

0

Downstream port 3 may have a removable device attached.

 

 

 

1

Downstream port 3 has a nonremovable device attached.

 

2

DR[2]

 

Device removable. DR[2] is the device removable bit for downstream port 2. Defines whether

 

 

 

downstream port 2 has a removable or nonremovable device.

 

 

 

0

Downstream port 2 may have a removable device attached.

 

 

 

1

Downstream port 2 has a nonremovable device attached.

 

1

DR[1]

 

Device removable. DR[1] is the device removable bit for downstream port 1. Defines whether

 

 

 

downstream port 1 has a removable or nonremovable device.

 

 

 

0

Downstream port 1 may have a removable device attached.

 

 

 

1

Downstream port 1 has a nonremovable device attached.

 

0

DR[0]

0

Device removable. DR[0] is reserved.

 

28

Universal Serial Bus OHCI Host Controller

SPRUFM8–September 2008

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Contents Users Guide Literature Number SPRUFM8 SeptemberSPRUFM8-September Contents List of Figures List of Tables Read This First Universal Serial Bus Ohci Host Controller Purpose of the PeripheralUSB1 Module Clock and Reset 2 USB1 Module Local Bus Clock and Local ResetInternal System Bus Clocks Needed by the USB1 Module 3 USB1 Module Bus 48-MHz Reference ClockUSB1 Module Differences From Ohci Specification for USB USB1 Module Open Host Controller Interface FunctionalityImplementation of Ohci Specification for USB Ohci USB Suspend StateUSB Host Controller Access to System Memory Ohci InterruptsPhysical Addressing MMUUSB Host Controller Registers HC Operating Mode Register Hccontrol Ohci Revision Number Register HcrevisionOhci Revision Number Register Hcrevision Field Descriptions REVControl list enable Periodic list enableControl ED per bulk ED Control EDs per bulk EDHC Command and Status Register Hccommandstatus SOCOCR BLF CLF HCR OCRRhsc FNO WDH HC Interrupt and Status Register HcinterruptstatusRhsc HC Interrupt Enable Register Hcinterruptenable MIEHC Interrupt Disable Register Hcinterruptdisable HC Hcaa Address Register Hchcca HC Current Periodic Register HcperiodcurrentedHC Hcaa Address Register Hchcca Field Descriptions HccaHC Head Control Register Hccontrolheaded Field Descriptions HC Head Control Register HccontrolheadedChed Cced HC Current Control Register HccontrolcurrentedController HC Head Bulk Register Hcbulkheaded HC Current Bulk Register HcbulkcurrentedHC Head Bulk Register Hcbulkheaded Field Descriptions HC Current Bulk Register Hcbulkcurrented Field DescriptionsHC Head Done Register Hcdonehead HC Frame Interval Register HcfmintervalHC Head Done Register Hcdonehead Field Descriptions HC Frame Interval Register Hcfminterval Field DescriptionsHC Frame Remaining Register Hcfmremaining HC Frame Number Register HcfmnumberHC Frame Number Register Hcfmnumber Field Descriptions FRTHC Periodic Start Register Hcperiodicstart HC Periodic Start Register HcperiodicstartHC Low-Speed Threshold Register Hclsthreshold LST628h Reserved 13-0HC Root Hub a Register Hcrhdescriptora HC Root Hub a Register Hcrhdescriptora Field DescriptionsPotpg Nocp Ocpm NPS PSM NDPHC Root Hub B Register Hcrhdescriptorb HC Root Hub B Register Hcrhdescriptorb Field DescriptionsPPCM3 PPCM2 PPCM1 PPCM0 PPCM3HC Root Hub Status Register Hcrhstatus HC Root Hub Status Register Hcrhstatus Field DescriptionsHC Port 1 Status and Control Register HCRHPORTSTATUS1 PRS/SPR HC Port 2 Status and Control Register HCRHPORTSTATUS2 Effect Port 2 current connect status has not changedWhen read as 0, USB reset is not being sent to port Begin signaling USB reset to portEnd of the USB reset sequence Write of 1 to this bit clears the port 2 port enable bitDSP Rfid