Texas Instruments TMS320C6747 DSP manual HC Head Done Register Hcdonehead

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Registers

3.13 HC Head Done Register (HCDONEHEAD)

The HC head done register (HCDONEHEAD) defines the physical address of the current head of the done TD queue. HCDONEHEAD is shown in Figure 14 and described in Table 14.

Figure 14. HC Head Done Register (HCDONEHEAD)

31			16
	DH
	R-0
15	4	3	0
DH			Reserved
R-0			R-0

LEGEND: R = Read only; -n= value after reset

Table 14. HC Head Done Register (HCDONEHEAD) Field Descriptions

Bit	Field	Value	Description
31-4	DH	0-FFF FFFFh	Physical address of the last TD that has added to the done queue. This field represents bits 31-4
			of the physical address of the top TD on the done TD queue. TDs are assumed to begin on a
			16-byte aligned address, so bits 3-0 of this pointer are assumed to be 0.
			A value of 0 indicates that there are no TDs on the done queue. This register is automatically
			updated by the USB host controller.
3-0	Reserved	0	Reserved

3.14 HC Frame Interval Register (HCFMINTERVAL)

The HC frame interval register (HCFMINTERVAL) defines the number of 12-MHZ clock pulses in each USB frame. HCFMINTERVAL is shown in Figure 15 and described in Table 15.

			Figure 15. HC Frame Interval Register (HCFMINTERVAL)
31	30			16
FIT				FSMPS
R/W-0				R/W-0
15	14	13		0
Reserved				FRAMEINTERVAL
R-0				R/W-2EDFh
LEGEND: R/W = Read/Write; R = Read only; -n= value after reset
		Table 15. HC Frame Interval Register (HCFMINTERVAL) Field Descriptions
Bit	Field		Value	Description
31	FIT		0-1	Frame interval toggle. The host controller driver must toggle this bit any time it changes
				the frame interval field.
30-16	FSMPS		0-7FFFh	Largest data packet. Largest data packet size allowed for full-speed packets, in bit times.
15-14	Reserved		0	Reserved
13-0	FRAMEINTERVAL		0-3FFFh	Frame interval. Number of 12-MHZ clocks in the USB frame. Nominally, this is set to
				11,999 (2EDFh) to give a 1-ms frame. The host controller driver can make minor changes
				to this field to attempt to manually synchronize with another clock source.
SPRUFM8–September 2008				Universal Serial Bus OHCI Host Controller	23
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Contents Literature Number SPRUFM8 September Users GuideSPRUFM8-September Contents List of Figures List of Tables Read This First Purpose of the Peripheral Universal Serial Bus Ohci Host Controller3 USB1 Module Bus 48-MHz Reference Clock USB1 Module Clock and Reset2 USB1 Module Local Bus Clock and Local Reset Internal System Bus Clocks Needed by the USB1 ModuleUSB1 Module Open Host Controller Interface Functionality USB1 Module Differences From Ohci Specification for USBOhci USB Suspend State Implementation of Ohci Specification for USBMMU USB Host Controller Access to System MemoryOhci Interrupts Physical AddressingUSB Host Controller Registers REV HC Operating Mode Register HccontrolOhci Revision Number Register Hcrevision Ohci Revision Number Register Hcrevision Field DescriptionsControl EDs per bulk ED Control list enablePeriodic list enable Control ED per bulk EDOCR HC Command and Status Register HccommandstatusSOC OCR BLF CLF HCRRhsc HC Interrupt and Status Register HcinterruptstatusRhsc FNO WDH MIE HC Interrupt Enable Register HcinterruptenableHC Interrupt Disable Register Hcinterruptdisable Hcca HC Hcaa Address Register HchccaHC Current Periodic Register Hcperiodcurrented HC Hcaa Address Register Hchcca Field DescriptionsChed HC Head Control Register HccontrolheadedHC Head Control Register Hccontrolheaded Field Descriptions Controller HC Current Control Register HccontrolcurrentedCced HC Current Bulk Register Hcbulkcurrented Field Descriptions HC Head Bulk Register HcbulkheadedHC Current Bulk Register Hcbulkcurrented HC Head Bulk Register Hcbulkheaded Field DescriptionsHC Frame Interval Register Hcfminterval Field Descriptions HC Head Done Register HcdoneheadHC Frame Interval Register Hcfminterval HC Head Done Register Hcdonehead Field DescriptionsFRT HC Frame Remaining Register HcfmremainingHC Frame Number Register Hcfmnumber HC Frame Number Register Hcfmnumber Field DescriptionsHC Periodic Start Register Hcperiodicstart HC Periodic Start Register HcperiodicstartReserved 13-0 HC Low-Speed Threshold Register HclsthresholdLST 628hNocp Ocpm NPS PSM NDP HC Root Hub a Register HcrhdescriptoraHC Root Hub a Register Hcrhdescriptora Field Descriptions PotpgPPCM3 HC Root Hub B Register HcrhdescriptorbHC Root Hub B Register Hcrhdescriptorb Field Descriptions PPCM3 PPCM2 PPCM1 PPCM0HC Root Hub Status Register Hcrhstatus Field Descriptions HC Root Hub Status Register HcrhstatusHC Port 1 Status and Control Register HCRHPORTSTATUS1 PRS/SPR Effect Port 2 current connect status has not changed HC Port 2 Status and Control Register HCRHPORTSTATUS2Write of 1 to this bit clears the port 2 port enable bit When read as 0, USB reset is not being sent to portBegin signaling USB reset to port End of the USB reset sequenceRfid DSP