Texas Instruments TMS320C6747 DSP manual HC Frame Remaining Register Hcfmremaining, Frt

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Registers

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3.15 HC Frame Remaining Register (HCFMREMAINING)

The HC frame remaining register (HCFMREMAINING) reports the number of full-speed bit times remaining in the current frame. HCFMREMAINING is shown in Figure 16 and described in Table 16.

 

 

Figure 16. HC Frame Remaining Register (HCFMREMAINING)

31

30

 

16

FRT

 

 

Reserved

R-0

 

 

R-0

15

14

13

0

Reserved

 

FR

R-0

 

 

R-0

LEGEND: R = Read only; -n= value after reset

 

 

Table 16. HC Frame Remaining Register (HCFMREMAINING) Field Descriptions

Bit

Field

Value

Description

31

FRT

0-1

Frame remaining toggle. This bit is loaded with the frame interval toggle bit every time the USB

 

 

 

host controller loads the frame interval field into the frame remaining field.

30-14

Reserved

0

Reserved

13-0

FR

0-3FFFh

Frame remaining. The number of full-speed bit times remaining in the current frame. This field is

 

 

 

automatically reloaded with the frame interval (FI) value in the HC frame interval register

 

 

 

(HCFMINTERVAL) at the beginning of every frame.

3.16 HC Frame Number Register (HCFMNUMBER)

The HC frame number register (HCFMNUMBER) reports the current USB frame number. HCFMNUMBER is shown in Figure 17 and described in Table 17.

 

Figure 17. HC Frame Number Register (HCFMNUMBER)

31

16

 

Reserved

 

R-0

15

0

 

FN

 

R-0

LEGEND: R = Read only; -n= value after reset

Table 17. HC Frame Number Register (HCFMNUMBER) Field Descriptions

Bit

Field

Value

Description

31-16

Reserved

0

Reserved

15-0

FN

0-FFFFh

Frame number. This field reports the current USB frame number. It is incremented when the frame

 

 

 

remaining field is reloaded with the frame interval (FI) value in the HC frame interval register

 

 

 

(HCFMINTERVAL). Frame number automatically rolls over from FFFFh to 0. After frame number is

 

 

 

incremented, its new value is written to the HCCA and the USB host controller sets the SOF

 

 

 

interrupt status bit and begins processing the ED lists.

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Universal Serial Bus OHCI Host Controller

SPRUFM8–September 2008

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Contents Users Guide Literature Number SPRUFM8 SeptemberSPRUFM8-September Contents List of Figures List of Tables Read This First Universal Serial Bus Ohci Host Controller Purpose of the PeripheralUSB1 Module Clock and Reset 2 USB1 Module Local Bus Clock and Local ResetInternal System Bus Clocks Needed by the USB1 Module 3 USB1 Module Bus 48-MHz Reference ClockUSB1 Module Differences From Ohci Specification for USB USB1 Module Open Host Controller Interface FunctionalityImplementation of Ohci Specification for USB Ohci USB Suspend StateUSB Host Controller Access to System Memory Ohci InterruptsPhysical Addressing MMUUSB Host Controller Registers HC Operating Mode Register Hccontrol Ohci Revision Number Register HcrevisionOhci Revision Number Register Hcrevision Field Descriptions REVControl list enable Periodic list enableControl ED per bulk ED Control EDs per bulk EDHC Command and Status Register Hccommandstatus SOCOCR BLF CLF HCR OCRHC Interrupt and Status Register Hcinterruptstatus Rhsc FNO WDHRhsc HC Interrupt Enable Register Hcinterruptenable MIEHC Interrupt Disable Register Hcinterruptdisable HC Hcaa Address Register Hchcca HC Current Periodic Register HcperiodcurrentedHC Hcaa Address Register Hchcca Field Descriptions HccaHC Head Control Register Hccontrolheaded HC Head Control Register Hccontrolheaded Field DescriptionsChed HC Current Control Register Hccontrolcurrented CcedController HC Head Bulk Register Hcbulkheaded HC Current Bulk Register HcbulkcurrentedHC Head Bulk Register Hcbulkheaded Field Descriptions HC Current Bulk Register Hcbulkcurrented Field DescriptionsHC Head Done Register Hcdonehead HC Frame Interval Register HcfmintervalHC Head Done Register Hcdonehead Field Descriptions HC Frame Interval Register Hcfminterval Field DescriptionsHC Frame Remaining Register Hcfmremaining HC Frame Number Register HcfmnumberHC Frame Number Register Hcfmnumber Field Descriptions FRTHC Periodic Start Register Hcperiodicstart HC Periodic Start Register HcperiodicstartHC Low-Speed Threshold Register Hclsthreshold LST628h Reserved 13-0HC Root Hub a Register Hcrhdescriptora HC Root Hub a Register Hcrhdescriptora Field DescriptionsPotpg Nocp Ocpm NPS PSM NDPHC Root Hub B Register Hcrhdescriptorb HC Root Hub B Register Hcrhdescriptorb Field DescriptionsPPCM3 PPCM2 PPCM1 PPCM0 PPCM3HC Root Hub Status Register Hcrhstatus HC Root Hub Status Register Hcrhstatus Field DescriptionsHC Port 1 Status and Control Register HCRHPORTSTATUS1 PRS/SPR HC Port 2 Status and Control Register HCRHPORTSTATUS2 Effect Port 2 current connect status has not changedWhen read as 0, USB reset is not being sent to port Begin signaling USB reset to portEnd of the USB reset sequence Write of 1 to this bit clears the port 2 port enable bitDSP Rfid
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