Texas Instruments TMS320C6747 DSP manual Read This First

Page 6

Preface

SPRUFM8–September 2008

Read This First

About This Manual

This document describes the universal serial bus OHCI host controller.

Notational Conventions

This document uses the following conventions.

∙Hexadecimal numbers are shown with the suffix h. For example, the following number is 40 hexadecimal (decimal 64): 40h.

∙Registers in this document are shown in figures and described in tables.

–Each register figure shows a rectangle divided into fields that represent the fields of the register. Each field is labeled with its bit name, its beginning and ending bit numbers above, and its read/write properties below. A legend explains the notation used for the properties.

–Reserved bits in a register figure designate a bit that is used for future device expansion.

Related Documentation From Texas Instruments

The following documents describe the TMS320C6745/C6747 DSP. Copies of these documents are available on the Internet at www.ti.com. Tip: Enter the literature number in the search box provided at www.ti.com.

The current documentation that describes the DSP, related peripherals, and other technical collateral, is available in the C6000 DSP product folder at: www.ti.com/c6000.

SPRUFE8 — TMS320C674x DSP CPU and Instruction Set Reference Guide. Describes the CPU architecture, pipeline, instruction set, and interrupts for the TMS320C674x digital signal processors (DSPs). The C674x DSP is an enhancement of the C64x+ and C67x+ DSPs with added functionality and an expanded instruction set.

SPRUFK4 — TMS320C6745/C6747 DSP System Reference Guide. Describes the System-on-Chip (SoC) including the DSP subsystem, system memory, device clocking, phase-locked loop controller (PLLC), power and sleep controller (PSC), power management, and system configuration module.

SPRUFK5 — TMS320C674x DSP Megamodule Reference Guide. Describes the TMS320C674x digital signal processor (DSP) megamodule. Included is a discussion on the internal direct memory access (IDMA) controller, the interrupt controller, the power-down controller, memory protection, bandwidth management, and the memory and cache.

SPRUFK9 — TMS320C6745/C6747 DSP Peripherals Overview Reference Guide. Provides an overview and briefly describes the peripherals available on the TMS320C6745/C6747 DSP.

SPRUG82 — TMS320C674x DSP Cache User's Guide. Explains the fundamentals of memory caches and describes how the two-level cache-based internal memory architecture in the TMS320C674x digital signal processor (DSP) can be efficiently used in DSP applications. Shows how to maintain coherence with external memory, how to use DMA to reduce memory latencies, and how to optimize your code to improve cache efficiency. The internal memory architecture in the C674x DSP is organized in a two-level hierarchy consisting of a dedicated program cache (L1P) and a dedicated data cache (L1D) on the first level. Accesses by the CPU to the these first level caches can complete without CPU pipeline stalls. If the data requested by the CPU is not contained in cache, it is fetched from the next lower memory level, L2 or external memory.

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Preface

SPRUFM8–September 2008

 

 

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Contents Users Guide Literature Number SPRUFM8 SeptemberSPRUFM8-September Contents List of Figures List of Tables Read This First Universal Serial Bus Ohci Host Controller Purpose of the PeripheralInternal System Bus Clocks Needed by the USB1 Module USB1 Module Clock and Reset2 USB1 Module Local Bus Clock and Local Reset 3 USB1 Module Bus 48-MHz Reference ClockUSB1 Module Differences From Ohci Specification for USB USB1 Module Open Host Controller Interface FunctionalityImplementation of Ohci Specification for USB Ohci USB Suspend StatePhysical Addressing USB Host Controller Access to System MemoryOhci Interrupts MMUUSB Host Controller Registers Ohci Revision Number Register Hcrevision Field Descriptions HC Operating Mode Register HccontrolOhci Revision Number Register Hcrevision REVControl ED per bulk ED Control list enablePeriodic list enable Control EDs per bulk EDOCR BLF CLF HCR HC Command and Status Register HccommandstatusSOC OCRHC Interrupt and Status Register Hcinterruptstatus Rhsc FNO WDHRhsc HC Interrupt Enable Register Hcinterruptenable MIEHC Interrupt Disable Register Hcinterruptdisable HC Hcaa Address Register Hchcca Field Descriptions HC Hcaa Address Register HchccaHC Current Periodic Register Hcperiodcurrented HccaHC Head Control Register Hccontrolheaded HC Head Control Register Hccontrolheaded Field DescriptionsChed HC Current Control Register Hccontrolcurrented CcedController HC Head Bulk Register Hcbulkheaded Field Descriptions HC Head Bulk Register HcbulkheadedHC Current Bulk Register Hcbulkcurrented HC Current Bulk Register Hcbulkcurrented Field DescriptionsHC Head Done Register Hcdonehead Field Descriptions HC Head Done Register HcdoneheadHC Frame Interval Register Hcfminterval HC Frame Interval Register Hcfminterval Field DescriptionsHC Frame Number Register Hcfmnumber Field Descriptions HC Frame Remaining Register HcfmremainingHC Frame Number Register Hcfmnumber FRTHC Periodic Start Register Hcperiodicstart HC Periodic Start Register Hcperiodicstart628h HC Low-Speed Threshold Register HclsthresholdLST Reserved 13-0Potpg HC Root Hub a Register HcrhdescriptoraHC Root Hub a Register Hcrhdescriptora Field Descriptions Nocp Ocpm NPS PSM NDPPPCM3 PPCM2 PPCM1 PPCM0 HC Root Hub B Register HcrhdescriptorbHC Root Hub B Register Hcrhdescriptorb Field Descriptions PPCM3HC Root Hub Status Register Hcrhstatus HC Root Hub Status Register Hcrhstatus Field DescriptionsHC Port 1 Status and Control Register HCRHPORTSTATUS1 PRS/SPR HC Port 2 Status and Control Register HCRHPORTSTATUS2 Effect Port 2 current connect status has not changedEnd of the USB reset sequence When read as 0, USB reset is not being sent to portBegin signaling USB reset to port Write of 1 to this bit clears the port 2 port enable bitDSP Rfid
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