Texas Instruments TMS320C6747 DSP manual USB1 Module Open Host Controller Interface Functionality

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Architecture

2.2USB1 Module Open Host Controller Interface Functionality

2.2.1OHCI Controller Overview

The Open HCI—Open Host Controller Interface Specification for USB, Release 1.0a defines a set of registers and data structures stored in system memory that control how a USB host controller interfaces to system software. This specification, in conjunction with the Universal Serial Bus Specification Version 2.0, defines most of the USB functionality that the USB host controller provides.

The OHCI Specification for USB focuses on two main aspects of the USB host controller hardware implementation: its register set and the memory data structures that define the appearance of USB bus activity. Other topics include interrupt generation, USB host controller state, USB frame management, and the hardware methods used to process the lists of data structures in system memory.

This document does not duplicate the information presented in the OHCI Specification for USB or the USB Specification. USB host controller users can refer to the USB Specification and the OHCI Specification for USB for detailed discussions of USB requirements and OHCI controller operation.

2.3USB1 Module Differences From OHCI Specification for USB

The USB1 Module OHCI compatible host controller implementation does not implement every aspect of the functionality defined in the OHCI Specification for USB. The differences focus on power switching, overcurrent reporting, and the OHCI ownership change interrupt. Other restrictions are imposed by the effects of the pin multiplexing options.

2.3.1Power Switching Output Pins Not Supported

The device does not provide pins that can be controlled directly by the USB host controller OHCI port power control features. The OHCI RHPORTSTATUS register port power control bits can be programmed by the USB host controller driver software, but this does not have any direct effect on any VBUS switching implemented on the board.

You can use software control of GPIO pins or other implementation-specific control mechanisms to control VBUS switching.

2.3.2Overcurrent Protection Input Pins Not Supported

The device does not provide any pins that allow the USB host controller OHCI RHPORTSTATUS overcurrent protection status bits to be directly controlled by external hardware.

You can use software monitoring of GPIO pins or other implementation-specific control mechanisms to report port overcurrent information to the USB host controller driver.

2.3.3No Ownership Change Interrupt

The USB host controller does not implement the OHCI ownership change interrupt.

SPRUFM8–September 2008

Universal Serial Bus OHCI Host Controller

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Contents Literature Number SPRUFM8 September Users GuideSPRUFM8-September Contents List of Figures List of Tables Read This First Purpose of the Peripheral Universal Serial Bus Ohci Host Controller2 USB1 Module Local Bus Clock and Local Reset USB1 Module Clock and ResetInternal System Bus Clocks Needed by the USB1 Module 3 USB1 Module Bus 48-MHz Reference ClockUSB1 Module Open Host Controller Interface Functionality USB1 Module Differences From Ohci Specification for USBOhci USB Suspend State Implementation of Ohci Specification for USBOhci Interrupts USB Host Controller Access to System MemoryPhysical Addressing MMUUSB Host Controller Registers Ohci Revision Number Register Hcrevision HC Operating Mode Register HccontrolOhci Revision Number Register Hcrevision Field Descriptions REVPeriodic list enable Control list enableControl ED per bulk ED Control EDs per bulk EDSOC HC Command and Status Register HccommandstatusOCR BLF CLF HCR OCRHC Interrupt and Status Register Hcinterruptstatus Rhsc FNO WDHRhsc MIE HC Interrupt Enable Register HcinterruptenableHC Interrupt Disable Register Hcinterruptdisable HC Current Periodic Register Hcperiodcurrented HC Hcaa Address Register HchccaHC Hcaa Address Register Hchcca Field Descriptions HccaHC Head Control Register Hccontrolheaded HC Head Control Register Hccontrolheaded Field DescriptionsChed HC Current Control Register Hccontrolcurrented CcedController HC Current Bulk Register Hcbulkcurrented HC Head Bulk Register HcbulkheadedHC Head Bulk Register Hcbulkheaded Field Descriptions HC Current Bulk Register Hcbulkcurrented Field DescriptionsHC Frame Interval Register Hcfminterval HC Head Done Register HcdoneheadHC Head Done Register Hcdonehead Field Descriptions HC Frame Interval Register Hcfminterval Field DescriptionsHC Frame Number Register Hcfmnumber HC Frame Remaining Register HcfmremainingHC Frame Number Register Hcfmnumber Field Descriptions FRTHC Periodic Start Register Hcperiodicstart HC Periodic Start Register HcperiodicstartLST HC Low-Speed Threshold Register Hclsthreshold628h Reserved 13-0HC Root Hub a Register Hcrhdescriptora Field Descriptions HC Root Hub a Register HcrhdescriptoraPotpg Nocp Ocpm NPS PSM NDPHC Root Hub B Register Hcrhdescriptorb Field Descriptions HC Root Hub B Register HcrhdescriptorbPPCM3 PPCM2 PPCM1 PPCM0 PPCM3HC Root Hub Status Register Hcrhstatus Field Descriptions HC Root Hub Status Register HcrhstatusHC Port 1 Status and Control Register HCRHPORTSTATUS1 PRS/SPR Effect Port 2 current connect status has not changed HC Port 2 Status and Control Register HCRHPORTSTATUS2Begin signaling USB reset to port When read as 0, USB reset is not being sent to portEnd of the USB reset sequence Write of 1 to this bit clears the port 2 port enable bitRfid DSP
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