Texas Instruments TMS320C6747 DSP manual Contents

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Contents

Preface			6
1	Introduction		7
	1.1	Purpose of the Peripheral	7
2	Architecture		8
	2.1	USB1 Module Clock and Reset	8
	2.2	USB1 Module Open Host Controller Interface Functionality	9
	2.3	USB1 Module Differences From OHCI Specification for USB	9
	2.4	Implementation of OHCI Specification for USB	10
	2.5	OHCI Interrupts	11
	2.6	USB Host Controller Access to System Memory	11
	2.7	Physical Addressing	11
3	Registers		12
	3.1	OHCI Revision Number Register (HCREVISION)	13
	3.2	HC Operating Mode Register (HCCONTROL)	13
	3.3	HC Command and Status Register (HCCOMMANDSTATUS)	15
	3.4	HC Interrupt and Status Register (HCINTERRUPTSTATUS)	16
	3.5	HC Interrupt Enable Register (HCINTERRUPTENABLE)	17
	3.6	HC Interrupt Disable Register (HCINTERRUPTDISABLE)	18
	3.7	HC HCAA Address Register (HCHCCA)	19
	3.8	HC Current Periodic Register (HCPERIODCURRENTED)	19
	3.9	HC Head Control Register (HCCONTROLHEADED)	20
	3.10	HC Current Control Register (HCCONTROLCURRENTED)	21
	3.11	HC Head Bulk Register (HCBULKHEADED)	22
	3.12	HC Current Bulk Register (HCBULKCURRENTED)	22
	3.13	HC Head Done Register (HCDONEHEAD)	23
	3.14	HC Frame Interval Register (HCFMINTERVAL)	23
	3.15	HC Frame Remaining Register (HCFMREMAINING)	24
	3.16	HC Frame Number Register (HCFMNUMBER)	24
	3.17	HC Periodic Start Register (HCPERIODICSTART)	25
	3.18	HC Low-Speed Threshold Register (HCLSTHRESHOLD)	26
	3.19	HC Root Hub A Register (HCRHDESCRIPTORA)	27
	3.20	HC Root Hub B Register (HCRHDESCRIPTORB)	28
	3.21	HC Root Hub Status Register (HCRHSTATUS)	29
	3.22	HC Port 1 Status and Control Register (HCRHPORTSTATUS1)	30
	3.23	HC Port 2 Status and Control Register (HCRHPORTSTATUS2)	32

SPRUFM8–September 2008

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Contents Literature Number SPRUFM8 September Users GuideSPRUFM8-September Contents List of Figures List of Tables Read This First Purpose of the Peripheral Universal Serial Bus Ohci Host Controller3 USB1 Module Bus 48-MHz Reference Clock USB1 Module Clock and Reset2 USB1 Module Local Bus Clock and Local Reset Internal System Bus Clocks Needed by the USB1 ModuleUSB1 Module Open Host Controller Interface Functionality USB1 Module Differences From Ohci Specification for USBOhci USB Suspend State Implementation of Ohci Specification for USBMMU USB Host Controller Access to System MemoryOhci Interrupts Physical AddressingUSB Host Controller Registers REV HC Operating Mode Register HccontrolOhci Revision Number Register Hcrevision Ohci Revision Number Register Hcrevision Field DescriptionsControl EDs per bulk ED Control list enablePeriodic list enable Control ED per bulk EDOCR HC Command and Status Register HccommandstatusSOC OCR BLF CLF HCRHC Interrupt and Status Register Hcinterruptstatus Rhsc FNO WDHRhsc MIE HC Interrupt Enable Register HcinterruptenableHC Interrupt Disable Register Hcinterruptdisable Hcca HC Hcaa Address Register HchccaHC Current Periodic Register Hcperiodcurrented HC Hcaa Address Register Hchcca Field DescriptionsHC Head Control Register Hccontrolheaded HC Head Control Register Hccontrolheaded Field DescriptionsChed HC Current Control Register Hccontrolcurrented CcedController HC Current Bulk Register Hcbulkcurrented Field Descriptions HC Head Bulk Register HcbulkheadedHC Current Bulk Register Hcbulkcurrented HC Head Bulk Register Hcbulkheaded Field DescriptionsHC Frame Interval Register Hcfminterval Field Descriptions HC Head Done Register HcdoneheadHC Frame Interval Register Hcfminterval HC Head Done Register Hcdonehead Field DescriptionsFRT HC Frame Remaining Register HcfmremainingHC Frame Number Register Hcfmnumber HC Frame Number Register Hcfmnumber Field DescriptionsHC Periodic Start Register Hcperiodicstart HC Periodic Start Register HcperiodicstartReserved 13-0 HC Low-Speed Threshold Register HclsthresholdLST 628hNocp Ocpm NPS PSM NDP HC Root Hub a Register HcrhdescriptoraHC Root Hub a Register Hcrhdescriptora Field Descriptions PotpgPPCM3 HC Root Hub B Register HcrhdescriptorbHC Root Hub B Register Hcrhdescriptorb Field Descriptions PPCM3 PPCM2 PPCM1 PPCM0HC Root Hub Status Register Hcrhstatus Field Descriptions HC Root Hub Status Register HcrhstatusHC Port 1 Status and Control Register HCRHPORTSTATUS1 PRS/SPR Effect Port 2 current connect status has not changed HC Port 2 Status and Control Register HCRHPORTSTATUS2Write of 1 to this bit clears the port 2 port enable bit When read as 0, USB reset is not being sent to portBegin signaling USB reset to port End of the USB reset sequenceRfid DSP