Texas Instruments TMS320C6747 DSP manual USB1 Module Clock and Reset

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Architecture

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2 Architecture

2.1USB1 Module Clock and Reset

The USB1 module requires that several different clocks are present before it can be accessed:

1.Internal system bus clocks for accesses by the ARM or DSP (Device SYSCLK2 and SYSCLK4)

2.Local bus clock to the USB Host controller (derived from SYSCLK4)

3.USB bus side 48-MHz reference clock must be present. Several options are available to source this clock.

2.1.1Internal System Bus Clocks Needed by the USB1 Module

The internal system bus clocks SYSCLK2 and SYSCLK4 are normally configured during the device reset process; as the device PLL controller is initialized. The USB host controller operates in the SYSCLK4 domain but SYSCLK2 since most of the device level bus infrastructure operates on the SYSCLK2 domain. Normally one or both of the host CPU clock domains (SYSCLK6 for the ARM and SYSCLK1 for the DSP) will be enabled as well.

2.1.2USB1 Module Local Bus Clock and Local Reset

The USB Host Controller actually operates from a local (gated) version of SYSCLK4. This allows the module be put into a low power state when not in use. The module also has its own local reset that is asserted during a device level reset and remains asserted until released by software. Additionally software can at any time assert a hardware reset on the USB Host Controller individually, causing it to reinitialize without affecting any of the other peripherals on the device.

Both the local clock and local reset of the USB Host Controller are under the control of the device level Power Sleep Controller 1 (PSC1) module. This module controls many local power sleep controller modules, and local power sleep controller 2 (LPSC2) of PSC1 controls the USB OHCI Host Controller.

2.1.3USB1 Module Bus 48-MHz Reference Clock

This device includes an integrated USB 1.1 Phy for the OHCI Host Controller's Root Hub (Port 0). This Phy requires a 48-MHz reference clock for proper operation. Two options are available to provide this reference clock:

∙Use the reference clock generated by the USB0 module integrated high-speed phy. The high-speed phy includes a phase locked loop (PLL) that is capable of generating a 48-MHz reference clock from multiple different input clock options. This method is probably the most convenient as it does not require an externally sourced clock, and the PLL in the USB0 module has flexibility in the frequency of its input clock. However when using this option, the USB0 phy must be operating in order to use the USB1 OHCI host controller. (This does not mean that the USB0 module must be running, only that its phy needs to be configured properly and enabled).

∙Provide the 48 MHz clock externally, on the USB_REFCLKIN pin.

For details on device level configuration of the 48-MHz reference clock, see the device clocking chapter in the TMS320C6745/C6747 DSP System Reference Guide (SPRUFK4).

The USB host controller completes its reset after the host controller clock is transitioned from disabled to enabled and the host controller reset is removed. After system software turns on the clock to the USB host controller and removes it from reset, it is necessary to wait until the USB host controller internal reset completes. To ensure that the USB host controller has completely reset, system software must wait until reads of both the HCREVISION register and the HCHCCA register return their correct reset default values.

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Universal Serial Bus OHCI Host Controller

SPRUFM8–September 2008

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Contents Users Guide Literature Number SPRUFM8 SeptemberSPRUFM8-September Contents List of Figures List of Tables Read This First Universal Serial Bus Ohci Host Controller Purpose of the PeripheralUSB1 Module Clock and Reset 2 USB1 Module Local Bus Clock and Local ResetInternal System Bus Clocks Needed by the USB1 Module 3 USB1 Module Bus 48-MHz Reference ClockUSB1 Module Differences From Ohci Specification for USB USB1 Module Open Host Controller Interface FunctionalityImplementation of Ohci Specification for USB Ohci USB Suspend StateUSB Host Controller Access to System Memory Ohci InterruptsPhysical Addressing MMUUSB Host Controller Registers HC Operating Mode Register Hccontrol Ohci Revision Number Register HcrevisionOhci Revision Number Register Hcrevision Field Descriptions REVControl list enable Periodic list enableControl ED per bulk ED Control EDs per bulk EDHC Command and Status Register Hccommandstatus SOCOCR BLF CLF HCR OCRRhsc HC Interrupt and Status Register HcinterruptstatusRhsc FNO WDH HC Interrupt Enable Register Hcinterruptenable MIEHC Interrupt Disable Register Hcinterruptdisable HC Hcaa Address Register Hchcca HC Current Periodic Register HcperiodcurrentedHC Hcaa Address Register Hchcca Field Descriptions HccaChed HC Head Control Register HccontrolheadedHC Head Control Register Hccontrolheaded Field Descriptions Controller HC Current Control Register HccontrolcurrentedCced HC Head Bulk Register Hcbulkheaded HC Current Bulk Register HcbulkcurrentedHC Head Bulk Register Hcbulkheaded Field Descriptions HC Current Bulk Register Hcbulkcurrented Field DescriptionsHC Head Done Register Hcdonehead HC Frame Interval Register HcfmintervalHC Head Done Register Hcdonehead Field Descriptions HC Frame Interval Register Hcfminterval Field DescriptionsHC Frame Remaining Register Hcfmremaining HC Frame Number Register HcfmnumberHC Frame Number Register Hcfmnumber Field Descriptions FRTHC Periodic Start Register Hcperiodicstart HC Periodic Start Register HcperiodicstartHC Low-Speed Threshold Register Hclsthreshold LST628h Reserved 13-0HC Root Hub a Register Hcrhdescriptora HC Root Hub a Register Hcrhdescriptora Field DescriptionsPotpg Nocp Ocpm NPS PSM NDPHC Root Hub B Register Hcrhdescriptorb HC Root Hub B Register Hcrhdescriptorb Field DescriptionsPPCM3 PPCM2 PPCM1 PPCM0 PPCM3HC Root Hub Status Register Hcrhstatus HC Root Hub Status Register Hcrhstatus Field DescriptionsHC Port 1 Status and Control Register HCRHPORTSTATUS1 PRS/SPR HC Port 2 Status and Control Register HCRHPORTSTATUS2 Effect Port 2 current connect status has not changedWhen read as 0, USB reset is not being sent to port Begin signaling USB reset to portEnd of the USB reset sequence Write of 1 to this bit clears the port 2 port enable bitDSP Rfid
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