Texas Instruments TMS320C6747 DSP manual HC Interrupt Disable Register Hcinterruptdisable

Page 18

Registers

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3.6HC Interrupt Disable Register (HCINTERRUPTDISABLE)

The HC interrupt disable register (HCINTERRUPTDISABLE) is used to clear bits in the HC interrupt enable register (HCINTERRUPTENABLE). HCINTERRUPTDISABLE is shown in Figure 7 and described in Table 7.

Figure 7. HC Interrupt Disable Register (HCINTERRUPTDISABLE)

31	30	29								16
MIE	OC		Reserved
R/W-0	R-0			R-0
15			7	6	5	4	3	2	1	0
		Reserved		RHSC	FNO	UE	RD	SF	WDH	SO
		R-0		R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n= value after reset

Table 7. HC Interrupt Disable Register (HCINTERRUPTDISABLE) Field Descriptions

Bit	Field	Value	Description
31	MIE		Master interrupt enable. Read always returns 0.
		0	No effect.
		1	Clears the MIE bit in the HC interrupt enable register (HCINTERRUPTENABLE).
30	OC	0-1	Ownership change.
29-7	Reserved	0	Reserved
6	RHSC		Root hub status change. Read always returns 0.
		0	No effect.
		1	Clears the RHSC bit in the HC interrupt enable register (HCINTERRUPTENABLE).
5	FNO		Frame number overflow. Read always returns 0.
		0	No effect.
		1	Clears the FNO bit in the HC interrupt enable register (HCINTERRUPTENABLE).
4	UE		Unrecoverable error. Read always returns 0.
		0	No effect.
		1	Clears the UE bit in the HC interrupt enable register (HCINTERRUPTENABLE).
3	RD		Resume detected. Read always returns 0.
		0	No effect.
		1	Clears the RD bit in the HC interrupt enable register (HCINTERRUPTENABLE).
2	SF		Start of frame. Read always returns 0.
		0	No effect.
		1	Clears the SF bit in the HC interrupt enable register (HCINTERRUPTENABLE).
1	WDH		Write done head. Read always returns 0.
		0	No effect.
		1	Clears the WDH bit in the HC interrupt enable register (HCINTERRUPTENABLE).
0	SO		Scheduling overrun. Read always returns 0.
		0	No effect.
		1	Clears the SO bit in the HC interrupt enable register (HCINTERRUPTENABLE).

18	Universal Serial Bus OHCI Host Controller	SPRUFM8–September 2008
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Contents Users Guide Literature Number SPRUFM8 SeptemberSPRUFM8-September Contents List of Figures List of Tables Read This First Universal Serial Bus Ohci Host Controller Purpose of the PeripheralInternal System Bus Clocks Needed by the USB1 Module USB1 Module Clock and Reset2 USB1 Module Local Bus Clock and Local Reset 3 USB1 Module Bus 48-MHz Reference ClockUSB1 Module Differences From Ohci Specification for USB USB1 Module Open Host Controller Interface FunctionalityImplementation of Ohci Specification for USB Ohci USB Suspend StatePhysical Addressing USB Host Controller Access to System MemoryOhci Interrupts MMUUSB Host Controller Registers Ohci Revision Number Register Hcrevision Field Descriptions HC Operating Mode Register HccontrolOhci Revision Number Register Hcrevision REVControl ED per bulk ED Control list enablePeriodic list enable Control EDs per bulk EDOCR BLF CLF HCR HC Command and Status Register HccommandstatusSOC OCRHC Interrupt and Status Register Hcinterruptstatus Rhsc FNO WDHRhsc HC Interrupt Enable Register Hcinterruptenable MIEHC Interrupt Disable Register Hcinterruptdisable HC Hcaa Address Register Hchcca Field Descriptions HC Hcaa Address Register HchccaHC Current Periodic Register Hcperiodcurrented HccaHC Head Control Register Hccontrolheaded HC Head Control Register Hccontrolheaded Field DescriptionsChed HC Current Control Register Hccontrolcurrented CcedController HC Head Bulk Register Hcbulkheaded Field Descriptions HC Head Bulk Register HcbulkheadedHC Current Bulk Register Hcbulkcurrented HC Current Bulk Register Hcbulkcurrented Field DescriptionsHC Head Done Register Hcdonehead Field Descriptions HC Head Done Register HcdoneheadHC Frame Interval Register Hcfminterval HC Frame Interval Register Hcfminterval Field DescriptionsHC Frame Number Register Hcfmnumber Field Descriptions HC Frame Remaining Register HcfmremainingHC Frame Number Register Hcfmnumber FRTHC Periodic Start Register Hcperiodicstart HC Periodic Start Register Hcperiodicstart628h HC Low-Speed Threshold Register HclsthresholdLST Reserved 13-0Potpg HC Root Hub a Register HcrhdescriptoraHC Root Hub a Register Hcrhdescriptora Field Descriptions Nocp Ocpm NPS PSM NDPPPCM3 PPCM2 PPCM1 PPCM0 HC Root Hub B Register HcrhdescriptorbHC Root Hub B Register Hcrhdescriptorb Field Descriptions PPCM3HC Root Hub Status Register Hcrhstatus HC Root Hub Status Register Hcrhstatus Field DescriptionsHC Port 1 Status and Control Register HCRHPORTSTATUS1 PRS/SPR HC Port 2 Status and Control Register HCRHPORTSTATUS2 Effect Port 2 current connect status has not changedEnd of the USB reset sequence When read as 0, USB reset is not being sent to portBegin signaling USB reset to port Write of 1 to this bit clears the port 2 port enable bitDSP Rfid