Texas Instruments TMS320C6747 DSP manual Universal Serial Bus Ohci Host Controller

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User's Guide

SPRUFM8–September 2008

Universal Serial Bus OHCI Host Controller

1Introduction

This document describes the universal serial bus OHCI host controller.

1.1Purpose of the Peripheral

The USB OHCI host controller (HC) is a single port controller that communicates with USB devices at the USB low-speed (1.5M bit-per-second maximum) and full-speed (12M bit-per-second maximum) data rates. It is compatible with the Universal Serial Bus Specification Revision 2.0 and the Open HCI—Open Host Controller Interface Specification for USB, Release 1.0a, available through the Compaq Computer Corporation web site, and hereafter called the OHCI Specification for USB. It is assumed that users of the USB host controller are already familiar with the USB Specification and OHCI Specification for USB.

The USB host controller implements the register set and makes use of the memory data structures defined in the OHCI Specification for USB. These registers and data structures are the mechanisms by which a USB host controller driver software package can control the USB host controller. The OHCI Specification for USB also defines how the USB host controller implementation must interact with those registers and data structures in system memory.

To reduce processor software and interrupt overhead, the USB host controller generates USB traffic based on data structures and data buffers stored in system memory. The USB host controller accesses these data structures without direct intervention by the processor using its bus master port. These data structures and data buffers can be located in internal or external system RAM.

The USB host controller provides an interrupt to both the ARM and DSP.

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Contents Literature Number SPRUFM8 September Users GuideSPRUFM8-September Contents List of Figures List of Tables Read This First Purpose of the Peripheral Universal Serial Bus Ohci Host Controller3 USB1 Module Bus 48-MHz Reference Clock USB1 Module Clock and Reset2 USB1 Module Local Bus Clock and Local Reset Internal System Bus Clocks Needed by the USB1 ModuleUSB1 Module Open Host Controller Interface Functionality USB1 Module Differences From Ohci Specification for USBOhci USB Suspend State Implementation of Ohci Specification for USBMMU USB Host Controller Access to System MemoryOhci Interrupts Physical AddressingUSB Host Controller Registers REV HC Operating Mode Register HccontrolOhci Revision Number Register Hcrevision Ohci Revision Number Register Hcrevision Field DescriptionsControl EDs per bulk ED Control list enablePeriodic list enable Control ED per bulk EDOCR HC Command and Status Register HccommandstatusSOC OCR BLF CLF HCRRhsc FNO WDH HC Interrupt and Status Register HcinterruptstatusRhsc MIE HC Interrupt Enable Register HcinterruptenableHC Interrupt Disable Register Hcinterruptdisable Hcca HC Hcaa Address Register HchccaHC Current Periodic Register Hcperiodcurrented HC Hcaa Address Register Hchcca Field DescriptionsHC Head Control Register Hccontrolheaded Field Descriptions HC Head Control Register HccontrolheadedChed Cced HC Current Control Register HccontrolcurrentedController HC Current Bulk Register Hcbulkcurrented Field Descriptions HC Head Bulk Register HcbulkheadedHC Current Bulk Register Hcbulkcurrented HC Head Bulk Register Hcbulkheaded Field DescriptionsHC Frame Interval Register Hcfminterval Field Descriptions HC Head Done Register HcdoneheadHC Frame Interval Register Hcfminterval HC Head Done Register Hcdonehead Field DescriptionsFRT HC Frame Remaining Register HcfmremainingHC Frame Number Register Hcfmnumber HC Frame Number Register Hcfmnumber Field DescriptionsHC Periodic Start Register Hcperiodicstart HC Periodic Start Register HcperiodicstartReserved 13-0 HC Low-Speed Threshold Register HclsthresholdLST 628hNocp Ocpm NPS PSM NDP HC Root Hub a Register HcrhdescriptoraHC Root Hub a Register Hcrhdescriptora Field Descriptions PotpgPPCM3 HC Root Hub B Register HcrhdescriptorbHC Root Hub B Register Hcrhdescriptorb Field Descriptions PPCM3 PPCM2 PPCM1 PPCM0HC Root Hub Status Register Hcrhstatus Field Descriptions HC Root Hub Status Register HcrhstatusHC Port 1 Status and Control Register HCRHPORTSTATUS1 PRS/SPR Effect Port 2 current connect status has not changed HC Port 2 Status and Control Register HCRHPORTSTATUS2Write of 1 to this bit clears the port 2 port enable bit When read as 0, USB reset is not being sent to portBegin signaling USB reset to port End of the USB reset sequenceRfid DSP