Texas Instruments TMS320F20x/F24x DSP manual Benefits of Embedded Flash Memory in a DSP System

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PRELIMINARY

Benefits of Embedded Flash Memory in a DSP System

1.3 Benefits of Embedded Flash Memory in a DSP System

The circuitry density of flash memory is about half that of conventional EE- PROM memory, making it possible to approach DRAM densities with flash memory. This increased density allows flash memory to be integrated with a CPU and other peripherals in a single 'F20x/F24x DSP chip. Embedded flash memory expands the capabilities of the 'F20x/F24x DSPs in the areas of proto- typing, integrated solutions, and field upgradeable designs.

Embedded flash memory facilitates system development and early field test- ing. Throughout the development process, the system software can be up- dated and reprogrammed into the flash memory for testing at various stages. Since flash is a non-volatile memory type, the resulting standalone prototype can be tested in the appropriate environment without the need for battery backup. In addition to its nonvolatile nature, embedded flash memory has the advantage of in-system programming. Unlike some discrete flash or EEPROM chips, embedded flash memory can be programmed without removing the de- vice from the system board. In fact, the embedded flash memory of 'F20x/F24x DSPs can be programmed using hardware emulators which are already an in- tegral part of the DSP development process; no external programming equip- ment is required.

The embedded flash memory of 'F20x/F24x DSPs also makes these devices ideal for highly integrated, low-cost systems. The initial investment involved with making a ROM memory is not justifiable for certain low-cost applications. Accordingly, when on-chip ROM is not an option, DSP system designers usu- ally resort to using expensive static RAM (SRAM), to store system software and data. The SRAM provides the fast access times required by the DSP, but has the disadvantage of being a volatile memory type. To address the issue of memory volatility, designers often use a low-cost EPROM or flash device to load the SRAM after system power-up. This approach is very expensive, and the increased chip count is often prohibitive. The 'F20x/F24x DSPs, with their on-chip flash memory modules, provide a single chip solution with nonvolatile memory that supports full speed DSP access rates.

Another benefit of embedded flash memory in a DSP system is remote repro- grammability. Field upgradeability is an extremely useful feature for em- bedded systems. For example, many modem manufacturers offer algorithm upgrades remotely, without requiring the modem to be removed from the host computer system. The same type of feature is also being offered for many handheld consumer products. Adding this capability to a product requires the addition of EEPROM or flash devices, which increase chip count and system cost. Since no external equipment is required to program the embedded flash memory of the 'F20x/F24x DSPs, these devices enable field upgradeability without impacting system cost.

PRELIMINARY

Introduction 1-5

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Contents Literature Number SPRU282 September Important Notice Read This First Preliminary Related Documentation From Texas Instruments Preliminary If You Need Assistance Viii Contents Contents Figures Tables Introduction Basic Concepts of Flash Memory Technology ±1. TMS320 Devices With On-Chip Flash Eeprom TMS320F20x/F24x Flash Module±1. TMS320F20x/F24x Program Space Memory Maps Benefits of Embedded Flash Memory in a DSP System Preliminary Topic Flash Operations and Control RegistersPreliminary Flash Operations and Control Registers ±1. Flash Memory Logic Levels During Programming and Erasing Accessing the Flash Module 1 TMS320F206 Flash Access-Control Register ±2. Memory Maps in Register and Array Access ModesOUT 2 TMS320F24x Flash Access-Control RegisterSegment Control Register Segctr Flash Module Control Registers±3. Segment Control Register Field Descriptions Write Address Register Wadrs Flash Test Register TSTWrite Data Register Wdata Read Modes Program Operation Erase Operation Recovering From Over-Erasure Flash-Write Operation Protecting the Array Reading From the Flash ArrayAlgorithm Implementations Software Considerations How the Algorithms Fit Into the Program-Erase-Reprogram Flow ±1. Algorithms in the Overall Flow ±2. The Programming Algorithm in the Overall Flow Programming or Clear AlgorithmPreliminary ±3. Programming or Clear Algorithm Flow Step Action Description Mask the data to program Preliminary ±4. Erase Algorithm in the Overall Flow Erase Algorithm±2. Steps for Applying One Erase Pulse Preliminary ±5. Erase Algorithm Flow ±6. Flash-Write Algorithm in the Overall Flow Flash-Write Algorithm±3. Steps for Applying One Flash-Write Pulse ±7. Flash-Write Algorithm Flow Preliminary Preliminary Assembly Source Listings Program Examples Header File for Constants and Variables, SVAR20.H Assembly Source for AlgorithmsBASE0 ErrorBASE+0 BASE1D5K ConstantsD7K DloopSegst Clear Algorithm, SCLR20.ASMSegend ProtectSplk #0,ERROR Gclr PROTECT,SEGST,SEGEND DELAY,REGS,ARRAYAR0 AR1Sacl Flst Exit Splk #1,ERRORLacl Fladrs NewrowSET Delay Call DELAY,*,AR6 Wait Stop Write Operation Splk Activate Write BIT Tblw SPAD1 Execute Command LARShutdown Write Operation Tblw SPAD1 Execute Command LAR Tblr FldataPrgbyte Call SETRDVER0 Tblw SPAD1 Execute Command LARLacl BASE2 Bcnd PBDONE,EQErase Algorithm, SERA20.ASM Erase Exebin Command Word Erase Command WordInverse Erase Command Word Flash Write Command WordSacl Flend Clrc OVMCall Setmode XoreraseInverase Splk #INVER,BASE0 Call Setmode Splk #STOP,BASE0Bldd Nextivers Lacl BASE1Flash Stop command, and Ffff for Wdata Flash-Write Algorithm, SFLW20.ASM Bldd #FLST,BASE1 MaxflwFlws Call DELAY,*,AR6 Call Array Access Flash Array DoneBcnd Flwrite SplkSetmode Call Lacl Tblw LAR Call Call RET LAR AR0,#MAXFLW CmprProgramming Algorithm, SPGM20.ASM AR3 PROTECT,DELAY,REGS,ARRAYAR4 GpgmjGpgmj Splk Setc Intm Globally Mask ALL Interrupts Splk #0,ERRORMask ALL Interrupts SUB Sacl BASE4Bcnd DONE, GT Rowdone Lacl FladrsLacl Fladrs Newrow Adjrow NEGSETRDVER0 Call Regs Access Flash Registers Shut Down Write Operation Tblw SPAD1 Execute Command LARPbend RET XOR FldataBcnd PBEND,EQ Subroutines Used By All Four Algorithms, SUTILS20.ASM SPAD2,FACCESS1 OUT SPAD2,FACCESS0OUT SPAD2,F24XACCS Lacc Flst SUBCallable Interface to Flash Algorithms SEGST,SEGEND,PROTECT GclrPARMS+1 PARMS+2Ersparams Lacl ErrorArstack ArprotectCall Flws Sacl ErscountLAR AR1,SVAR1 1PROTECTCall Gpgmj Popd *+Assembly Code for TMS320F206 Sample Assembly Code to Erase and Reprogram the TMS320F206PARMS+1 SUB Memory Sections Block B2Psaram DLY PsaramSample C Code to Erase and Reprogram the TMS320F206 Linker Command File for TMS320F206 Sample C Code FLASH1 FLASH0BLKB2 Block B2 DsaramAssembly Code for TMS320F240 Sample Assembly Code to Erase and Reprogram the TMS320F240Wdcr RticrCKCR0 CKCR1PORRST, PLLRST, Illrst SWRST, Wdrst Lacl Syssr Accl = Syssr LDP #DPPF1Sacl Syssr LDP #PARMS SplkDaram LDP #PARMS B0PGM Linker Command File for TMS320F240 Sample Assembly CodeExtram Extram 0 /******Delay Subroutine Rev1.003/98 JGC Linker Command File for TMS320F240 Sample C Code B0DAT Block B2 DsramLacl Wdcr Function for Disabling TMS320F240 Watchdog TimerCompute Length Sacl Wdcr Functions for Initializing the TMS320F240Pshd SyscrSacl Wdtcr Index Assembly code SERA2x.ASM Described 10 to Margin Role in single program pulse WRITE/ERASE field Described
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