Texas Instruments TMS320F20x/F24x DSP manual Rticr, Wdcr, CKCR0, CKCR1, Syssr, DPPF1

Page 93

PRELIMINARY

Sample Assembly Code to Erase and Reprogram the TMS320F240

;**Variables included from flash algorithms.

.include ºsvar20.hº

;Variable declarations

.ref

GCLR

;References clear algo.

.ref

GPGMJ

;References program algo.

.ref

GERS

;References erase algo.

.ref

FLWS

;References flash±write algo.

;**Parameters used by flash algorithms.

.def

PRG_bufaddr, PRG_paddr

.def

PRG_length, PARMS

.def SEG_ST,SEG_END,PROTECT ;**F240 Register definitions

RTICR

.set

07027h

;RTI Control Register

WDCR

.set

07029h

;WD Control Register

CKCR0

.set

0702Bh

;Clock Control Register 0

CKCR1

.set

0702Dh

;Clock Control Register 1

SYSSR

.set

0701Ah

;System Module Status Register

DP_PF1

.set

224

;page 1 of peripheral file

 

 

 

;(7000h/80h)

*************************************************************

VARS: .usect ºPRG_dataº,16 ;This is an uninitialized data

*

;section required by the standard *

;flash algos for temporary

*

;variables. Pointers to this

*

;space are hardcoded in SVAR20.H, *

;and variables are init'd at

*

;run time.

*

*************************************************************

PARMS: .usect ºPRG_parmº,10 ;This is an uninitialized data

*

;section that is used for

*

;temporary variables and for

*

;passing parameters to the flash

*

;algorithms.

*

*************************************************************

PROTECT .set PARMS ;Segment enable bits.*

**************************************************************

*****Parameters needed for Programming algorithm. ***

*************************************************************

PRG_bufaddr

.set

PARMS+1

;Addr of buffer for pgm data. *

PRG_paddr

.set

PARMS+2

;1st flash addr to program.

*

PRG_length

.set

PARMS+3

;Length of block to program.

*

*************************************************************

***Parameters needed for CLEAR, ERASE, and FLW algorithms. **

*************************************************************

SEG_ST

.set

PARMS+4

;Segment

start address.

*

SEG_END

.set

PARMS+5

;Segment

end address.

*

*************************************************************

****Other misc variables.****

*************************************************************

ERS_COUNT .set PARMS+6 ;Used for erase fail count. *

*************************************************************

.text

*************************************************************

**

First, initialize the key F240 registers for use with

*

**

the EVM.

*

*************************************************************

PRELIMINARY

Assembly Source Listings and Program Examples

A-41

Page 92 Page 94
Image 93
Page 92 Page 94
Contents Literature Number SPRU282 September Important Notice Read This First Preliminary Related Documentation From Texas Instruments Preliminary If You Need Assistance Viii Contents Contents Figures Tables Introduction Basic Concepts of Flash Memory Technology ±1. TMS320 Devices With On-Chip Flash Eeprom TMS320F20x/F24x Flash Module±1. TMS320F20x/F24x Program Space Memory Maps Benefits of Embedded Flash Memory in a DSP System Preliminary Topic Flash Operations and Control RegistersPreliminary Flash Operations and Control Registers ±1. Flash Memory Logic Levels During Programming and Erasing Accessing the Flash Module 1 TMS320F206 Flash Access-Control Register ±2. Memory Maps in Register and Array Access ModesOUT 2 TMS320F24x Flash Access-Control RegisterSegment Control Register Segctr Flash Module Control Registers±3. Segment Control Register Field Descriptions Write Address Register Wadrs Flash Test Register TSTWrite Data Register Wdata Read Modes Program Operation Erase Operation Recovering From Over-Erasure Flash-Write Operation Protecting the Array Reading From the Flash ArrayAlgorithm Implementations Software Considerations How the Algorithms Fit Into the Program-Erase-Reprogram Flow ±1. Algorithms in the Overall Flow ±2. The Programming Algorithm in the Overall Flow Programming or Clear AlgorithmPreliminary ±3. Programming or Clear Algorithm Flow Step Action Description Mask the data to program Preliminary ±4. Erase Algorithm in the Overall Flow Erase Algorithm±2. Steps for Applying One Erase Pulse Preliminary ±5. Erase Algorithm Flow ±6. Flash-Write Algorithm in the Overall Flow Flash-Write Algorithm±3. Steps for Applying One Flash-Write Pulse ±7. Flash-Write Algorithm Flow Preliminary Preliminary Assembly Source Listings Program Examples Header File for Constants and Variables, SVAR20.H Assembly Source for AlgorithmsBASE0 ErrorBASE+0 BASE1D5K ConstantsD7K DloopSegst Clear Algorithm, SCLR20.ASMSegend ProtectSplk #0,ERROR Gclr PROTECT,SEGST,SEGEND DELAY,REGS,ARRAYAR0 AR1Sacl Flst Exit Splk #1,ERRORLacl Fladrs NewrowSET Delay Call DELAY,*,AR6 Wait Stop Write Operation Splk Activate Write BIT Tblw SPAD1 Execute Command LARShutdown Write Operation Tblw SPAD1 Execute Command LAR Tblr FldataPrgbyte Call SETRDVER0 Tblw SPAD1 Execute Command LARLacl BASE2 Bcnd PBDONE,EQErase Algorithm, SERA20.ASM Erase Exebin Command Word Erase Command WordInverse Erase Command Word Flash Write Command WordSacl Flend Clrc OVMCall Setmode XoreraseInverase Splk #INVER,BASE0 Call Setmode Splk #STOP,BASE0Bldd Nextivers Lacl BASE1Flash Stop command, and Ffff for Wdata Flash-Write Algorithm, SFLW20.ASM Maxflw FlwsBldd #FLST,BASE1 Call DELAY,*,AR6 Call Array Access Flash Array DoneBcnd Flwrite SplkSetmode Call Lacl Tblw LAR Call Call RET LAR AR0,#MAXFLW CmprProgramming Algorithm, SPGM20.ASM AR3 PROTECT,DELAY,REGS,ARRAYAR4 GpgmjGpgmj Splk Setc Intm Globally Mask ALL Interrupts Splk #0,ERRORMask ALL Interrupts SUB Sacl BASE4Bcnd DONE, GT Rowdone Lacl FladrsLacl Fladrs Newrow Adjrow NEGSETRDVER0 Call Regs Access Flash Registers Shut Down Write Operation Tblw SPAD1 Execute Command LARXOR Fldata Bcnd PBEND,EQPbend RET Subroutines Used By All Four Algorithms, SUTILS20.ASM SPAD2,FACCESS1 OUT SPAD2,FACCESS0OUT SPAD2,F24XACCS Lacc Flst SUBCallable Interface to Flash Algorithms SEGST,SEGEND,PROTECT GclrPARMS+1 PARMS+2Ersparams Lacl ErrorArstack ArprotectCall Flws Sacl ErscountLAR AR1,SVAR1 1PROTECTCall Gpgmj Popd *+Assembly Code for TMS320F206 Sample Assembly Code to Erase and Reprogram the TMS320F206PARMS+1 SUB Memory Sections Block B2Psaram DLY PsaramSample C Code to Erase and Reprogram the TMS320F206 Linker Command File for TMS320F206 Sample C Code FLASH1 FLASH0BLKB2 Block B2 DsaramAssembly Code for TMS320F240 Sample Assembly Code to Erase and Reprogram the TMS320F240Wdcr RticrCKCR0 CKCR1PORRST, PLLRST, Illrst SWRST, Wdrst Lacl Syssr Accl = Syssr LDP #DPPF1Sacl Syssr LDP #PARMS SplkDaram LDP #PARMS Linker Command File for TMS320F240 Sample Assembly Code ExtramB0PGM Extram 0 /******Delay Subroutine Rev1.003/98 JGC Linker Command File for TMS320F240 Sample C Code B0DAT Block B2 DsramFunction for Disabling TMS320F240 Watchdog Timer Compute LengthLacl Wdcr Sacl Wdcr Functions for Initializing the TMS320F240Pshd SyscrSacl Wdtcr Index Assembly code SERA2x.ASM Described 10 to Margin Role in single program pulse WRITE/ERASE field Described
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