Texas Instruments TMS320F20x/F24x DSP manual Assembly code SERA2x.ASM Described 10 to

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Index

PRELIMINARY


erase algorithm
assembly code (SERA2x.ASM)							A-10
described	3-10 to 3-13
flow diagram		3-13
in overall flow			3-10
erase() function (C code listing)						A-27
erase operation
described	2-14
following flash±write operation							2-15
frequency range				3-12
logic levels		2-4
role of WDATA			2-11
VER1 read mode				2-12
verification of erased bits					2-12
worst±case voltage for reading erased cell 2-12
erase protection			3-11
erase pulse	2-14
example for TMS320F206
assembly code				A-32, A-40
C code that calls flash.asm						A-37, A-47
linker command file A-35, A-38, A-45, A-48
execute bit (EXE)
described	2-9
in mechanism for array protection								2-16
location in SEG_CTR register							2-8
relation to erase pulse 2-14
relation to flash±write pulse						2-15, 3-14
relation to program pulse					2-13
role in single erase pulse					3-11
role in single flash±write pulse							3-15
role in single program pulse						3-9
execute key bits (KEY1, KEY0)
described	2-9
in mechanism for array protection								2-16
location in SEG_CTR register							2-8
role in single erase pulse					3-11
role in single flash±write pulse							3-15
role in single program pulse						3-9
extending a read			3-5, 3-17

F

flash memory size 1-3 flash module 1-3

flash operation (block operation) 1-2

flash±write algorithm

assembly code (SFLW2x.ASM) A-15


described	3-14
flow diagram		3-16
in overall flow		3-14
flash±write operation
described	1-2, 2-15
similarity to erase 2-15
flash±write pulse		2-15, 3-14
frequency range
erasing 3-12
flash±write	3-17
programming		3-5

G

global parameters in the calling code A-2

H

header file for constants and variables (SVAR2x.H) A-2

I

IN instruction 2-7

inverse±erase read mode 2-12, 2-15, 3-15

K

KEY1, KEY0 bits described 2-9

in mechanism for array protection 2-16

location in SEG_CTR register	2-8
role in single erase pulse 3-11
role in single flash±write pulse	3-15

role in single program pulse 3-9

L

limited number of bits programmed at one time 2-13

linker command files
for TMS320F206 sample assembly code		A-35
for TMS320F206 sample C code	A-38
for TMS320F240 sample assembly code		A-45
for TMS320F240 sample C code	A-48

Index-2

PRELIMINARY

Image 106

Contents Literature Number SPRU282 September Important Notice Read This First Preliminary Related Documentation From Texas Instruments Preliminary If You Need Assistance Viii Contents Contents Figures Tables Introduction Basic Concepts of Flash Memory Technology TMS320F20x/F24x Flash Module ±1. TMS320 Devices With On-Chip Flash Eeprom±1. TMS320F20x/F24x Program Space Memory Maps Benefits of Embedded Flash Memory in a DSP System Preliminary Flash Operations and Control Registers TopicPreliminary Flash Operations and Control Registers ±1. Flash Memory Logic Levels During Programming and Erasing Accessing the Flash Module ±2. Memory Maps in Register and Array Access Modes 1 TMS320F206 Flash Access-Control Register2 TMS320F24x Flash Access-Control Register OUTFlash Module Control Registers Segment Control Register Segctr±3. Segment Control Register Field Descriptions Flash Test Register TST Write Address Register WadrsWrite Data Register Wdata Read Modes Program Operation Erase Operation Recovering From Over-Erasure Flash-Write Operation Reading From the Flash Array Protecting the ArrayAlgorithm Implementations Software Considerations How the Algorithms Fit Into the Program-Erase-Reprogram Flow ±1. Algorithms in the Overall Flow Programming or Clear Algorithm ±2. The Programming Algorithm in the Overall FlowPreliminary ±3. Programming or Clear Algorithm Flow Step Action Description Mask the data to program Preliminary Erase Algorithm ±4. Erase Algorithm in the Overall Flow±2. Steps for Applying One Erase Pulse Preliminary ±5. Erase Algorithm Flow Flash-Write Algorithm ±6. Flash-Write Algorithm in the Overall Flow±3. Steps for Applying One Flash-Write Pulse ±7. Flash-Write Algorithm Flow Preliminary Preliminary Assembly Source Listings Program Examples Assembly Source for Algorithms Header File for Constants and Variables, SVAR20.HBASE+0 ErrorBASE0 BASE1D7K ConstantsD5K DloopSegend Clear Algorithm, SCLR20.ASMSegst ProtectAR0 Gclr PROTECT,SEGST,SEGEND DELAY,REGS,ARRAYSplk #0,ERROR AR1Lacl Fladrs Exit Splk #1,ERRORSacl Flst NewrowShutdown Write Operation Tblw SPAD1 Execute Command LAR Activate Write BIT Tblw SPAD1 Execute Command LARSET Delay Call DELAY,*,AR6 Wait Stop Write Operation Splk Tblr FldataLacl BASE2 Tblw SPAD1 Execute Command LARPrgbyte Call SETRDVER0 Bcnd PBDONE,EQErase Algorithm, SERA20.ASM Inverse Erase Command Word Erase Command WordErase Exebin Command Word Flash Write Command WordCall Setmode Clrc OVMSacl Flend XoreraseBldd Splk #STOP,BASE0Inverase Splk #INVER,BASE0 Call Setmode Nextivers Lacl BASE1Flash Stop command, and Ffff for Wdata Flash-Write Algorithm, SFLW20.ASM Flws MaxflwBldd #FLST,BASE1 Bcnd Call Array Access Flash Array DoneCall DELAY,*,AR6 Flwrite SplkLAR AR0,#MAXFLW Cmpr Setmode Call Lacl Tblw LAR Call Call RETProgramming Algorithm, SPGM20.ASM AR4 PROTECT,DELAY,REGS,ARRAYAR3 GpgmjMask ALL Interrupts Setc Intm Globally Mask ALL Interrupts Splk #0,ERRORGpgmj Splk SUB Sacl BASE4Lacl Fladrs Newrow Rowdone Lacl FladrsBcnd DONE, GT Adjrow NEGShut Down Write Operation Tblw SPAD1 Execute Command LAR SETRDVER0 Call Regs Access Flash RegistersBcnd PBEND,EQ XOR FldataPbend RET Subroutines Used By All Four Algorithms, SUTILS20.ASM OUT SPAD2,F24XACCS OUT SPAD2,FACCESS0SPAD2,FACCESS1 Lacc Flst SUBCallable Interface to Flash Algorithms PARMS+1 GclrSEGST,SEGEND,PROTECT PARMS+2Arstack Lacl ErrorErsparams ArprotectLAR AR1,SVAR1 Sacl ErscountCall Flws 1PROTECTPopd *+ Call GpgmjSample Assembly Code to Erase and Reprogram the TMS320F206 Assembly Code for TMS320F206PARMS+1 SUB Memory Psaram Block B2Sections DLY PsaramSample C Code to Erase and Reprogram the TMS320F206 Linker Command File for TMS320F206 Sample C Code BLKB2 FLASH0FLASH1 Block B2 DsaramSample Assembly Code to Erase and Reprogram the TMS320F240 Assembly Code for TMS320F240CKCR0 RticrWdcr CKCR1Sacl Syssr LDP #DPPF1PORRST, PLLRST, Illrst SWRST, Wdrst Lacl Syssr Accl = Syssr LDP #PARMS SplkDaram LDP #PARMS Extram Linker Command File for TMS320F240 Sample Assembly CodeB0PGM Extram 0 /******Delay Subroutine Rev1.003/98 JGC Linker Command File for TMS320F240 Sample C Code Block B2 Dsram B0DATCompute Length Function for Disabling TMS320F240 Watchdog TimerLacl Wdcr Pshd Functions for Initializing the TMS320F240Sacl Wdcr SyscrSacl Wdtcr Index Assembly code SERA2x.ASM Described 10 to Margin Role in single program pulse WRITE/ERASE field Described