Texas Instruments TMS320F20x/F24x DSP manual ±3. Segment Control Register Field Descriptions

Page 27

PRELIMINARY

Flash Module Control Registers

Table 2±3. Segment Control Register Field Descriptions

Bits

Name

Description

 

 

 

15±8

SEG7±SEG0

Segment enable bits. Each of these bits protects the specified segment against pro-

 

 

gramming or enables programming for the specified segment in the array. Any number

 

 

of segments (from 0 to 7 in any combination) can be enabled at any one time. See

 

 

Table 2±4 for segment address ranges. EXE must be cleared to modify the SEGx bits.

 

 

SEGx = 1 enables programming of the corresponding segment.

 

 

SEGx = 0 protects the segment from programming.

7

Reserved

This bit is not affected by writes, and reads of this bit are undefined.

6±5

KEY1, KEY0

Execute key bits. A binary value of 10 must be written to these bits in the same DSP

 

 

core access in which the EXE bit is set for the selected operation (erase, program, or

 

 

flash-write) to start. KEY1 and KEY0 must be cleared in the same write access that

 

 

clears EXE. These bits are used as additional protection against inadvertent program-

 

 

ming or erasure of the array. These bits are read as 0s.

4±3

VER0, VER1

Verify bits. These bits select special read modes used to verify proper erasure or pro-

 

 

gramming.

 

 

Possible values:

 

 

00: Normal read mode

 

 

01: Verify 1s (VER1) read mode to verify margin of 1s for proper erasure

 

 

10: Verify 0s (VER0) read mode to verify margin of 0s for proper programming

 

 

11: Inverse-read mode; tests for bits erased into depletion

2±1

WRITE/ERASE

Write/erase enable field. These bits select the program, erase, or flash-write operation.

 

 

However, modification of the array data does not actually start until the EXE bit is set.

 

 

Reset clears these bits to zero.

 

 

Possible values:

 

 

00: Read operation is enabled. These bit values are required to read the array.

 

 

01: Erase operation is enabled

 

 

10: Write operation is enabled

 

 

11: Flash-write operation is enabled

0

EXE

Execute bit. In conjunction with WRITE/ERASE, KEY1, and KEY0, this bit controls the

 

 

program, erase, and flash-write operations. Setting EXE starts and stops program-

 

 

ming and erasing of the flash array. The KEY1 and KEY0 bits must be written in the

 

 

same write access that sets EXE, and EXE must be cleared in the same write access

 

 

that clears KEY1 and KEY0. EXE must be cleared to modify the SEGx bits.

 

 

Note:

The segment enable bits are not intended for protection during the erase or flash-write operations. During these opera-

 

tions, all segments must be enabled.

PRELIMINARY

Flash Operations and Control Registers

2-9

Image 27
Contents Literature Number SPRU282 September Important Notice Read This First Preliminary Related Documentation From Texas Instruments Preliminary If You Need Assistance Viii Contents Contents Figures Tables Introduction Basic Concepts of Flash Memory Technology ±1. TMS320 Devices With On-Chip Flash Eeprom TMS320F20x/F24x Flash Module±1. TMS320F20x/F24x Program Space Memory Maps Benefits of Embedded Flash Memory in a DSP System Preliminary Topic Flash Operations and Control RegistersPreliminary Flash Operations and Control Registers ±1. Flash Memory Logic Levels During Programming and Erasing Accessing the Flash Module 1 TMS320F206 Flash Access-Control Register ±2. Memory Maps in Register and Array Access ModesOUT 2 TMS320F24x Flash Access-Control RegisterSegment Control Register Segctr Flash Module Control Registers±3. Segment Control Register Field Descriptions Write Address Register Wadrs Flash Test Register TSTWrite Data Register Wdata Read Modes Program Operation Erase Operation Recovering From Over-Erasure Flash-Write Operation Protecting the Array Reading From the Flash ArrayAlgorithm Implementations Software Considerations How the Algorithms Fit Into the Program-Erase-Reprogram Flow ±1. Algorithms in the Overall Flow ±2. The Programming Algorithm in the Overall Flow Programming or Clear AlgorithmPreliminary ±3. Programming or Clear Algorithm Flow Step Action Description Mask the data to program Preliminary ±4. Erase Algorithm in the Overall Flow Erase Algorithm±2. Steps for Applying One Erase Pulse Preliminary ±5. Erase Algorithm Flow ±6. Flash-Write Algorithm in the Overall Flow Flash-Write Algorithm±3. Steps for Applying One Flash-Write Pulse ±7. Flash-Write Algorithm Flow Preliminary Preliminary Assembly Source Listings Program Examples Header File for Constants and Variables, SVAR20.H Assembly Source for AlgorithmsBASE1 ErrorBASE0 BASE+0Dloop ConstantsD5K D7KProtect Clear Algorithm, SCLR20.ASMSegst SegendAR1 Gclr PROTECT,SEGST,SEGEND DELAY,REGS,ARRAYSplk #0,ERROR AR0Newrow Exit Splk #1,ERRORSacl Flst Lacl FladrsTblr Fldata Activate Write BIT Tblw SPAD1 Execute Command LARSET Delay Call DELAY,*,AR6 Wait Stop Write Operation Splk Shutdown Write Operation Tblw SPAD1 Execute Command LARBcnd PBDONE,EQ Tblw SPAD1 Execute Command LARPrgbyte Call SETRDVER0 Lacl BASE2Erase Algorithm, SERA20.ASM Flash Write Command Word Erase Command WordErase Exebin Command Word Inverse Erase Command WordXorerase Clrc OVMSacl Flend Call SetmodeNextivers Lacl BASE1 Splk #STOP,BASE0Inverase Splk #INVER,BASE0 Call Setmode BlddFlash Stop command, and Ffff for Wdata Flash-Write Algorithm, SFLW20.ASM Maxflw FlwsBldd #FLST,BASE1 Flwrite Splk Call Array Access Flash Array DoneCall DELAY,*,AR6 BcndSetmode Call Lacl Tblw LAR Call Call RET LAR AR0,#MAXFLW CmprProgramming Algorithm, SPGM20.ASM Gpgmj PROTECT,DELAY,REGS,ARRAYAR3 AR4SUB Sacl BASE4 Setc Intm Globally Mask ALL Interrupts Splk #0,ERRORGpgmj Splk Mask ALL InterruptsAdjrow NEG Rowdone Lacl FladrsBcnd DONE, GT Lacl Fladrs NewrowSETRDVER0 Call Regs Access Flash Registers Shut Down Write Operation Tblw SPAD1 Execute Command LARXOR Fldata Bcnd PBEND,EQPbend RET Subroutines Used By All Four Algorithms, SUTILS20.ASM Lacc Flst SUB OUT SPAD2,FACCESS0SPAD2,FACCESS1 OUT SPAD2,F24XACCSCallable Interface to Flash Algorithms PARMS+2 GclrSEGST,SEGEND,PROTECT PARMS+1Arprotect Lacl ErrorErsparams Arstack1PROTECT Sacl ErscountCall Flws LAR AR1,SVAR1Call Gpgmj Popd *+Assembly Code for TMS320F206 Sample Assembly Code to Erase and Reprogram the TMS320F206PARMS+1 SUB Memory DLY Psaram Block B2Sections PsaramSample C Code to Erase and Reprogram the TMS320F206 Linker Command File for TMS320F206 Sample C Code Block B2 Dsaram FLASH0FLASH1 BLKB2Assembly Code for TMS320F240 Sample Assembly Code to Erase and Reprogram the TMS320F240CKCR1 RticrWdcr CKCR0LDP #PARMS Splk LDP #DPPF1PORRST, PLLRST, Illrst SWRST, Wdrst Lacl Syssr Accl = Syssr Sacl SyssrDaram LDP #PARMS Linker Command File for TMS320F240 Sample Assembly Code ExtramB0PGM Extram 0 /******Delay Subroutine Rev1.003/98 JGC Linker Command File for TMS320F240 Sample C Code B0DAT Block B2 DsramFunction for Disabling TMS320F240 Watchdog Timer Compute LengthLacl Wdcr Syscr Functions for Initializing the TMS320F240Sacl Wdcr PshdSacl Wdtcr Index Assembly code SERA2x.ASM Described 10 to Margin Role in single program pulse WRITE/ERASE field Described