Texas Instruments TMS320F20x/F24x DSP manual AR3, AR4, Gpgmj, Protect,Delay,Regs,Array

Page 72

Assembly Source for Algorithms

PRELIMINARY

* bits. For example, if the flash is programmed using a

*

* CLKOUT period of 50 ns, the flash can be reliably read

*

*

back over the CLKOUT period range of 50

ns to 150 ns

*

*

(6.67MHz±20 MHz). The programming pulse

duration is

*

* 100 us, and a maximum of 150 pulses is applied per row. *

*

 

 

*

* The following variables are used for temp storage:

*

*

AR0

Used for comparisons

*

*

AR1

Used for pgm pulse count

*

*

AR2

Used for row banz loop

*

*

AR3

Used for buffer addr index

*

*

AR4

Used for flash address.

*

*

AR6

Parameter passed to Delay

*

*

SPAD1

Flash program and STOP commands

*

*

SPAD2

Flash program + EXE command

*

*

FL_ADRS

Used for flash address

*

*

FL_DATA

Used for flash data

*

*

BASE_0

Used for row±done flag

*

*

BASE_1

Used for row start address

*

*

BASE_2

Used for row length±1

*

*

BASE_3

Used for buffer/row start addr

*

*

BASE_4

Used for destination end addr

*

*

BASE_5

Used for byte mask

*

*************************************************************

.include

ºsvar20.hº

*

 

 

 

MAX_PGM

.set

150

;Allow only 150 pulses per row.

VER0

.set

010h

;VER0 command.

WR_CMND

.set

4

;Write command.

WR_EXE

.set

045h

;Write EXEBIN command.

STOP

.set

0

;Reset command.

 

.def

GPGMJ

 

 

.ref

PRG_bufaddr,PRG_length,PRG_paddr

 

.ref

PROTECT,DELAY,REGS,ARRAY

 

.sect

ºfl_prgº

*********************************************************

* GPGMJ: This routine programs all or part of

*

*

the flash as specified by the variables:

*

*

PRG_paddr

Destination start address

*

*

PRG_length

Source buffer length

*

*

PRG_bufaddr

Buffer start address

*

*

 

 

 

*

* The following variables are used for temp

*

*

storage:

 

 

*

*

AR0

Used for comparisons

*

*

AR1

Used for pgm pulse count

*

*

AR2

Used for row banz loop

*

*

AR3

Used for buffer addr index

*

*

FL_ADRS

Used for flash address

*

*

FL_DATA

Used for flash data

*

*

BASE_0

Used for row±done flag

*

*

BASE_1

Used for row start address

*

*

BASE_2

Used for row length±1

*

A-20

PRELIMINARY

Image 72
Contents Literature Number SPRU282 September Important Notice Read This First Preliminary Related Documentation From Texas Instruments Preliminary If You Need Assistance Viii Contents Contents Figures Tables Introduction Basic Concepts of Flash Memory Technology TMS320F20x/F24x Flash Module ±1. TMS320 Devices With On-Chip Flash Eeprom±1. TMS320F20x/F24x Program Space Memory Maps Benefits of Embedded Flash Memory in a DSP System Preliminary Flash Operations and Control Registers TopicPreliminary Flash Operations and Control Registers ±1. Flash Memory Logic Levels During Programming and Erasing Accessing the Flash Module ±2. Memory Maps in Register and Array Access Modes 1 TMS320F206 Flash Access-Control Register2 TMS320F24x Flash Access-Control Register OUTFlash Module Control Registers Segment Control Register Segctr±3. Segment Control Register Field Descriptions Flash Test Register TST Write Address Register WadrsWrite Data Register Wdata Read Modes Program Operation Erase Operation Recovering From Over-Erasure Flash-Write Operation Reading From the Flash Array Protecting the ArrayAlgorithm Implementations Software Considerations How the Algorithms Fit Into the Program-Erase-Reprogram Flow ±1. Algorithms in the Overall Flow Programming or Clear Algorithm ±2. The Programming Algorithm in the Overall FlowPreliminary ±3. Programming or Clear Algorithm Flow Step Action Description Mask the data to program Preliminary Erase Algorithm ±4. Erase Algorithm in the Overall Flow±2. Steps for Applying One Erase Pulse Preliminary ±5. Erase Algorithm Flow Flash-Write Algorithm ±6. Flash-Write Algorithm in the Overall Flow±3. Steps for Applying One Flash-Write Pulse ±7. Flash-Write Algorithm Flow Preliminary Preliminary Assembly Source Listings Program Examples Assembly Source for Algorithms Header File for Constants and Variables, SVAR20.HError BASE0BASE+0 BASE1Constants D5KD7K DloopClear Algorithm, SCLR20.ASM SegstSegend ProtectGclr PROTECT,SEGST,SEGEND DELAY,REGS,ARRAY Splk #0,ERRORAR0 AR1Exit Splk #1,ERROR Sacl FlstLacl Fladrs NewrowActivate Write BIT Tblw SPAD1 Execute Command LAR SET Delay Call DELAY,*,AR6 Wait Stop Write Operation SplkShutdown Write Operation Tblw SPAD1 Execute Command LAR Tblr FldataTblw SPAD1 Execute Command LAR Prgbyte Call SETRDVER0Lacl BASE2 Bcnd PBDONE,EQErase Algorithm, SERA20.ASM Erase Command Word Erase Exebin Command WordInverse Erase Command Word Flash Write Command WordClrc OVM Sacl FlendCall Setmode XoreraseSplk #STOP,BASE0 Inverase Splk #INVER,BASE0 Call SetmodeBldd Nextivers Lacl BASE1Flash Stop command, and Ffff for Wdata Flash-Write Algorithm, SFLW20.ASM Maxflw FlwsBldd #FLST,BASE1 Call Array Access Flash Array Done Call DELAY,*,AR6Bcnd Flwrite SplkLAR AR0,#MAXFLW Cmpr Setmode Call Lacl Tblw LAR Call Call RETProgramming Algorithm, SPGM20.ASM PROTECT,DELAY,REGS,ARRAY AR3AR4 GpgmjSetc Intm Globally Mask ALL Interrupts Splk #0,ERROR Gpgmj SplkMask ALL Interrupts SUB Sacl BASE4Rowdone Lacl Fladrs Bcnd DONE, GTLacl Fladrs Newrow Adjrow NEGShut Down Write Operation Tblw SPAD1 Execute Command LAR SETRDVER0 Call Regs Access Flash RegistersXOR Fldata Bcnd PBEND,EQPbend RET Subroutines Used By All Four Algorithms, SUTILS20.ASM OUT SPAD2,FACCESS0 SPAD2,FACCESS1OUT SPAD2,F24XACCS Lacc Flst SUBCallable Interface to Flash Algorithms Gclr SEGST,SEGEND,PROTECTPARMS+1 PARMS+2Lacl Error ErsparamsArstack ArprotectSacl Erscount Call FlwsLAR AR1,SVAR1 1PROTECTPopd *+ Call GpgmjSample Assembly Code to Erase and Reprogram the TMS320F206 Assembly Code for TMS320F206PARMS+1 SUB Memory Block B2 SectionsPsaram DLY PsaramSample C Code to Erase and Reprogram the TMS320F206 Linker Command File for TMS320F206 Sample C Code FLASH0 FLASH1BLKB2 Block B2 DsaramSample Assembly Code to Erase and Reprogram the TMS320F240 Assembly Code for TMS320F240Rticr WdcrCKCR0 CKCR1LDP #DPPF1 PORRST, PLLRST, Illrst SWRST, Wdrst Lacl Syssr Accl = SyssrSacl Syssr LDP #PARMS SplkDaram LDP #PARMS Linker Command File for TMS320F240 Sample Assembly Code ExtramB0PGM Extram 0 /******Delay Subroutine Rev1.003/98 JGC Linker Command File for TMS320F240 Sample C Code Block B2 Dsram B0DATFunction for Disabling TMS320F240 Watchdog Timer Compute LengthLacl Wdcr Functions for Initializing the TMS320F240 Sacl WdcrPshd SyscrSacl Wdtcr Index Assembly code SERA2x.ASM Described 10 to Margin Role in single program pulse WRITE/ERASE field Described