Texas Instruments TMS320F20x/F24x DSP manual ±3. Steps for Applying One Flash-Write Pulse

PRELIMINARY

Flash-Write Algorithm

Table 3±3. Steps for Applying One Flash-Write Pulse

Steps Action Description

1 Power up the VCCP pin.

Set the VCCP pin to VDD. If the VCCP pin for the flash module to be re- covered is not set to VDD, then the flash-write operation will not be ef-

fective.

2Activate the flash-write mode and enable all seg- ments.

3Wait for the internally gener- ated supply voltage stabi- lization time.

Set the WRITE/ERASE field to 10 and set SEG0±SEG7 in the SEG_CTR register. The flash module must be in register access mode (see section 2.2).

The CPU executes a delay loop for the td(FLW-MODE²) time period.

4Initiate the flash-write pulse. Load the EXE, KEY1, and KEY0 bits with 1, 1, and 0, respectively. All three bits must be loaded in the same write cycle.

The segment enable bits and WRITE/ERASE field must also be main- tained.

5	Delay	for	the flash-write	The CPU executes a delay loop for the t	²	time period.
	pulse time.				d(FLW )
6	Terminate the flash-write			Clear all bits in the SEG_CTR register (load SEG_CTR with 0000h).
	pulse.
7	Delay	for	mode deselect	CPU executes a delay loop for the td(BUSY² ) time period.
	time.

²See the device data sheet for the timing parameter values.

The flash-write algorithm consists of multiple iterations of a loop with one flash- write pulse applied in each iteration. At the beginning of each iteration, a deple- tion test is performed to determine if a flash-write pulse is required. Figure 3±7 shows the flow of the flash-write algorithm.

The flash-write operation uses the inverse-erase read mode to detect bits that are in depletion mode. For more information about the inverse-erase read mode, see section 2.4, Read Modes, on page 2-12.

PRELIMINARY Algorithm Implementations and Software Considerations 3-15