Texas Instruments TMS320F20x/F24x DSP manual Related Documentation From Texas Instruments

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PRELIMINARY

Related Documentation From Texas Instruments

Related Documentation From Texas Instruments

The following books describe the 'F20x/24x and related support tools. To ob- tain a copy of any of these TI documents, call the Texas Instruments Literature Response Center at (800) 477±8924. When ordering, please identify the book by its title and literature number.

TMS320C24x DSP Controllers Reference Set, Volume 1: CPU, System,

and Instruction Set (literature number SPRU160) describes the TMS320C24x 16-bit, fixed-point, digital signal processor controller. Covered are its architecture, internal register structure, data and program addressing, and instruction set. Also includes instruction set comparisons and design considerations for using the XDS510 emulator.

TMS320C24x DSP Controllers Reference Set Volume 2: Peripheral

Library and Specific Devices (literature number SPRU161) describes the peripherals available on the TMS320C24x digital signal processor controllers and their operation. Also described are specific device configurations of the 'C24x family.

TMS320C240, TMS320F240 DSP Controllers (literature number SPRS042) data sheet contains the electrical and timing specifications for these devices, as well as signal descriptions and pinouts for all of the available packages.

TMS320C2x/C2xx/C5x Optimizing C Compiler User's Guide (literature number SPRU024) describes the 'C2x/C2xx/C5x C compiler. This C compiler accepts ANSI standard C source code and produces TMS320 assembly language source code for the 'C2x, 'C2xx, and 'C5x genera- tions of devices.

TMS320F206 Digital Signal Processor (literature number SPRS050) data sheet contains the electrical and timing specifications for the 'F206 device, as well as signal descriptions and the pinout.

TMS320F241, TMS320C241, TMS320C242 DSP Controllers (literature number SPRS063) data sheet contains the electrical and timing specifications for the 'F241, 'C241, and 'C242 devices, as well as signal descriptions and pinouts.

TMS320F243 DSP Controller (literature number SPRS064) data sheet contains the electrical and timing specifications for the 'F243 device, as well as signal descriptions and the pinout.

TMS320C2xx User's Guide (literature number SPRU127) discusses the hardware aspects of the 'C2xx 16-bit, fixed-point digital signal proces- sors. It describes the architecture, the instruction set, and the on-chip pe- ripherals.

PRELIMINARY

Read This First

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Contents Literature Number SPRU282 September Important Notice Read This First Preliminary Related Documentation From Texas Instruments Preliminary If You Need Assistance Viii Contents Contents Figures Tables Introduction Basic Concepts of Flash Memory Technology ±1. TMS320 Devices With On-Chip Flash Eeprom TMS320F20x/F24x Flash Module±1. TMS320F20x/F24x Program Space Memory Maps Benefits of Embedded Flash Memory in a DSP System Preliminary Topic Flash Operations and Control RegistersPreliminary Flash Operations and Control Registers ±1. Flash Memory Logic Levels During Programming and Erasing Accessing the Flash Module 1 TMS320F206 Flash Access-Control Register ±2. Memory Maps in Register and Array Access ModesOUT 2 TMS320F24x Flash Access-Control RegisterSegment Control Register Segctr Flash Module Control Registers±3. Segment Control Register Field Descriptions Write Address Register Wadrs Flash Test Register TSTWrite Data Register Wdata Read Modes Program Operation Erase Operation Recovering From Over-Erasure Flash-Write Operation Protecting the Array Reading From the Flash ArrayAlgorithm Implementations Software Considerations How the Algorithms Fit Into the Program-Erase-Reprogram Flow ±1. Algorithms in the Overall Flow ±2. The Programming Algorithm in the Overall Flow Programming or Clear AlgorithmPreliminary ±3. Programming or Clear Algorithm Flow Step Action Description Mask the data to program Preliminary ±4. Erase Algorithm in the Overall Flow Erase Algorithm±2. Steps for Applying One Erase Pulse Preliminary ±5. Erase Algorithm Flow ±6. Flash-Write Algorithm in the Overall Flow Flash-Write Algorithm±3. Steps for Applying One Flash-Write Pulse ±7. Flash-Write Algorithm Flow Preliminary Preliminary Assembly Source Listings Program Examples Header File for Constants and Variables, SVAR20.H Assembly Source for AlgorithmsBASE0 ErrorBASE+0 BASE1D5K ConstantsD7K DloopSegst Clear Algorithm, SCLR20.ASMSegend ProtectSplk #0,ERROR Gclr PROTECT,SEGST,SEGEND DELAY,REGS,ARRAYAR0 AR1Sacl Flst Exit Splk #1,ERRORLacl Fladrs NewrowSET Delay Call DELAY,*,AR6 Wait Stop Write Operation Splk Activate Write BIT Tblw SPAD1 Execute Command LARShutdown Write Operation Tblw SPAD1 Execute Command LAR Tblr FldataPrgbyte Call SETRDVER0 Tblw SPAD1 Execute Command LARLacl BASE2 Bcnd PBDONE,EQErase Algorithm, SERA20.ASM Erase Exebin Command Word Erase Command WordInverse Erase Command Word Flash Write Command WordSacl Flend Clrc OVMCall Setmode XoreraseInverase Splk #INVER,BASE0 Call Setmode Splk #STOP,BASE0Bldd Nextivers Lacl BASE1Flash Stop command, and Ffff for Wdata Flash-Write Algorithm, SFLW20.ASM Bldd #FLST,BASE1 MaxflwFlws Call DELAY,*,AR6 Call Array Access Flash Array DoneBcnd Flwrite SplkSetmode Call Lacl Tblw LAR Call Call RET LAR AR0,#MAXFLW CmprProgramming Algorithm, SPGM20.ASM AR3 PROTECT,DELAY,REGS,ARRAYAR4 GpgmjGpgmj Splk Setc Intm Globally Mask ALL Interrupts Splk #0,ERRORMask ALL Interrupts SUB Sacl BASE4Bcnd DONE, GT Rowdone Lacl FladrsLacl Fladrs Newrow Adjrow NEGSETRDVER0 Call Regs Access Flash Registers Shut Down Write Operation Tblw SPAD1 Execute Command LARPbend RET XOR FldataBcnd PBEND,EQ Subroutines Used By All Four Algorithms, SUTILS20.ASM SPAD2,FACCESS1 OUT SPAD2,FACCESS0OUT SPAD2,F24XACCS Lacc Flst SUBCallable Interface to Flash Algorithms SEGST,SEGEND,PROTECT GclrPARMS+1 PARMS+2Ersparams Lacl ErrorArstack ArprotectCall Flws Sacl ErscountLAR AR1,SVAR1 1PROTECTCall Gpgmj Popd *+Assembly Code for TMS320F206 Sample Assembly Code to Erase and Reprogram the TMS320F206PARMS+1 SUB Memory Sections Block B2Psaram DLY PsaramSample C Code to Erase and Reprogram the TMS320F206 Linker Command File for TMS320F206 Sample C Code FLASH1 FLASH0BLKB2 Block B2 DsaramAssembly Code for TMS320F240 Sample Assembly Code to Erase and Reprogram the TMS320F240Wdcr RticrCKCR0 CKCR1PORRST, PLLRST, Illrst SWRST, Wdrst Lacl Syssr Accl = Syssr LDP #DPPF1Sacl Syssr LDP #PARMS SplkDaram LDP #PARMS B0PGM Linker Command File for TMS320F240 Sample Assembly CodeExtram Extram 0 /******Delay Subroutine Rev1.003/98 JGC Linker Command File for TMS320F240 Sample C Code B0DAT Block B2 DsramLacl Wdcr Function for Disabling TMS320F240 Watchdog TimerCompute Length Sacl Wdcr Functions for Initializing the TMS320F240Pshd SyscrSacl Wdtcr Index Assembly code SERA2x.ASM Described 10 to Margin Role in single program pulse WRITE/ERASE field Described
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