Texas Instruments TMS320F20x/F24x DSP manual TMS320F20x/F24x Flash Module

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PRELIMINARY

TMS320F20x/F24x Flash Module

1.2 TMS320F20x/F24x Flash Module

The 'F20x/F24x flash EEPROM is implemented with one or two independent flash memory modules of 8K or 16K words. Each flash module is composed of a flash memory array, four control registers, and circuitry that produces ana- log voltages for programming and erasing. The flash array size of the TMS320F206 and TMS320F240 is 16K ×16 bits, while the TMS320F241 and TMS320F243 incorporate an 8K × 16-bit flash array (see Table 1±1). Unlike most discrete flash memories, the 'F20x/F24x flash module does not require a dedicated state machine, because the algorithms for programming and eras- ing the flash are executed in software by the DSP core. The use of these so- phisticated, adaptive programming algorithms results in reduced chip size and greater programming flexibility. In addition, the application code can manage the use of the flash memory without the requirement of external programming equipment.

Table 1±1. TMS320 Devices With On-Chip Flash EEPROM

Device	Array Size	Total Flash Memory

TMS320F206	16K	32K²
TMS320F240	16K	16K
TMS320F241	8K	8K
TMS320F243	8K	8K

²Each array can be independently erased.

PRELIMINARY

Introduction 1-3

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Contents Literature Number SPRU282 September Important Notice Read This First Preliminary Related Documentation From Texas Instruments Preliminary If You Need Assistance Viii Contents Contents Figures Tables Introduction Basic Concepts of Flash Memory Technology ±1. TMS320 Devices With On-Chip Flash Eeprom TMS320F20x/F24x Flash Module±1. TMS320F20x/F24x Program Space Memory Maps Benefits of Embedded Flash Memory in a DSP System Preliminary Topic Flash Operations and Control RegistersPreliminary Flash Operations and Control Registers ±1. Flash Memory Logic Levels During Programming and Erasing Accessing the Flash Module 1 TMS320F206 Flash Access-Control Register ±2. Memory Maps in Register and Array Access ModesOUT 2 TMS320F24x Flash Access-Control RegisterSegment Control Register Segctr Flash Module Control Registers±3. Segment Control Register Field Descriptions Write Address Register Wadrs Flash Test Register TSTWrite Data Register Wdata Read Modes Program Operation Erase Operation Recovering From Over-Erasure Flash-Write Operation Protecting the Array Reading From the Flash ArrayAlgorithm Implementations Software Considerations How the Algorithms Fit Into the Program-Erase-Reprogram Flow ±1. Algorithms in the Overall Flow ±2. The Programming Algorithm in the Overall Flow Programming or Clear AlgorithmPreliminary ±3. Programming or Clear Algorithm Flow Step Action Description Mask the data to program Preliminary ±4. Erase Algorithm in the Overall Flow Erase Algorithm±2. Steps for Applying One Erase Pulse Preliminary ±5. Erase Algorithm Flow ±6. Flash-Write Algorithm in the Overall Flow Flash-Write Algorithm±3. Steps for Applying One Flash-Write Pulse ±7. Flash-Write Algorithm Flow Preliminary Preliminary Assembly Source Listings Program Examples Header File for Constants and Variables, SVAR20.H Assembly Source for AlgorithmsBASE1 ErrorBASE0 BASE+0Dloop ConstantsD5K D7KProtect Clear Algorithm, SCLR20.ASMSegst SegendAR1 Gclr PROTECT,SEGST,SEGEND DELAY,REGS,ARRAYSplk #0,ERROR AR0Newrow Exit Splk #1,ERRORSacl Flst Lacl FladrsTblr Fldata Activate Write BIT Tblw SPAD1 Execute Command LARSET Delay Call DELAY,*,AR6 Wait Stop Write Operation Splk Shutdown Write Operation Tblw SPAD1 Execute Command LARBcnd PBDONE,EQ Tblw SPAD1 Execute Command LARPrgbyte Call SETRDVER0 Lacl BASE2Erase Algorithm, SERA20.ASM Flash Write Command Word Erase Command WordErase Exebin Command Word Inverse Erase Command WordXorerase Clrc OVMSacl Flend Call SetmodeNextivers Lacl BASE1 Splk #STOP,BASE0Inverase Splk #INVER,BASE0 Call Setmode BlddFlash Stop command, and Ffff for Wdata Flash-Write Algorithm, SFLW20.ASM Maxflw FlwsBldd #FLST,BASE1 Flwrite Splk Call Array Access Flash Array DoneCall DELAY,*,AR6 BcndSetmode Call Lacl Tblw LAR Call Call RET LAR AR0,#MAXFLW CmprProgramming Algorithm, SPGM20.ASM Gpgmj PROTECT,DELAY,REGS,ARRAYAR3 AR4SUB Sacl BASE4 Setc Intm Globally Mask ALL Interrupts Splk #0,ERRORGpgmj Splk Mask ALL InterruptsAdjrow NEG Rowdone Lacl FladrsBcnd DONE, GT Lacl Fladrs NewrowSETRDVER0 Call Regs Access Flash Registers Shut Down Write Operation Tblw SPAD1 Execute Command LARXOR Fldata Bcnd PBEND,EQPbend RET Subroutines Used By All Four Algorithms, SUTILS20.ASM Lacc Flst SUB OUT SPAD2,FACCESS0SPAD2,FACCESS1 OUT SPAD2,F24XACCSCallable Interface to Flash Algorithms PARMS+2 GclrSEGST,SEGEND,PROTECT PARMS+1Arprotect Lacl ErrorErsparams Arstack1PROTECT Sacl ErscountCall Flws LAR AR1,SVAR1Call Gpgmj Popd *+Assembly Code for TMS320F206 Sample Assembly Code to Erase and Reprogram the TMS320F206PARMS+1 SUB Memory DLY Psaram Block B2Sections PsaramSample C Code to Erase and Reprogram the TMS320F206 Linker Command File for TMS320F206 Sample C Code Block B2 Dsaram FLASH0FLASH1 BLKB2Assembly Code for TMS320F240 Sample Assembly Code to Erase and Reprogram the TMS320F240CKCR1 RticrWdcr CKCR0LDP #PARMS Splk LDP #DPPF1PORRST, PLLRST, Illrst SWRST, Wdrst Lacl Syssr Accl = Syssr Sacl SyssrDaram LDP #PARMS Linker Command File for TMS320F240 Sample Assembly Code ExtramB0PGM Extram 0 /******Delay Subroutine Rev1.003/98 JGC Linker Command File for TMS320F240 Sample C Code B0DAT Block B2 DsramFunction for Disabling TMS320F240 Watchdog Timer Compute LengthLacl Wdcr Syscr Functions for Initializing the TMS320F240Sacl Wdcr PshdSacl Wdtcr Index Assembly code SERA2x.ASM Described 10 to Margin Role in single program pulse WRITE/ERASE field Described