Texas Instruments TMS320F20x/F24x DSP manual XOR Fldata, Bcnd PBEND,EQ, Pbend RET

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Assembly Source for Algorithms

PRELIMINARY

LACL		FL_ST		;ACC => FLASH		*
SPLK		#VER0,SPAD1		;ACTIVATE VER0		*
TBLW		SPAD1		;EXECUTE COMMAND		*
LAR		AR6,#D10		;SET DELAY		*
CALL	DELAY,*,AR6		;WAIT			*
CALL	ARRAY		;ACCESS FLASH ARRAY			*
LACL		FL_ADRS		;POINT TO ADRS		*
TBLR		FL_DATA		;GET FLASH WORD 1x read		*
TBLR		FL_DATA		;	2x read	*
TBLR		FL_DATA		;	3x read	*
CALL	REGS		;ACCESS FLASH REGISTERS			*
LACL		FL_ST		;ACC => FLASH		*
SPLK		#STOP,SPAD1		;DEACTIVATE VER0		*
TBLW		SPAD1		;EXECUTE COMMAND		*
LAR		AR6,#D10		;SET DELAY		*
CALL	DELAY,*,AR6		;WAIT			*
CALL	ARRAY		;ACCESS FLASH ARRAY			*
RET		;RETURN TO CALLING SEQUENCE				*

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*PRG_BYTE: Programs hi or lo byte depending on*

*	byte mask (BASE_5).		*
*************************************************
PRG_BYTE:
	CALL	SET_RD_VER0	;Read word at VER0 level.
	MAR	*,AR3	;ARP ±> buffer addr index.
	LACL	*	;Get word to program.
	XOR	FL_DATA	;Xor with read±back value.
	AND	BASE_5	;Mask off hi/lo byte.
	BCND	PB_END,EQ	;If zero then done.
	XOR	#0FFFFh	;else, mask off good bits.
	SACL	FL_DATA	;New data.
	CALL	EXE_PGM	;PGM Pulse.
	SPLK	#0,BASE_0	;Set row done flag = 0(False).
PB_END RET

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A-24	PRELIMINARY

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Contents Literature Number SPRU282 September Important Notice Read This First Preliminary Related Documentation From Texas Instruments Preliminary If You Need Assistance Viii Contents Contents Figures Tables Introduction Basic Concepts of Flash Memory Technology TMS320F20x/F24x Flash Module ±1. TMS320 Devices With On-Chip Flash Eeprom±1. TMS320F20x/F24x Program Space Memory Maps Benefits of Embedded Flash Memory in a DSP System Preliminary Flash Operations and Control Registers TopicPreliminary Flash Operations and Control Registers ±1. Flash Memory Logic Levels During Programming and Erasing Accessing the Flash Module ±2. Memory Maps in Register and Array Access Modes 1 TMS320F206 Flash Access-Control Register2 TMS320F24x Flash Access-Control Register OUTFlash Module Control Registers Segment Control Register Segctr±3. Segment Control Register Field Descriptions Flash Test Register TST Write Address Register WadrsWrite Data Register Wdata Read Modes Program Operation Erase Operation Recovering From Over-Erasure Flash-Write Operation Reading From the Flash Array Protecting the ArrayAlgorithm Implementations Software Considerations How the Algorithms Fit Into the Program-Erase-Reprogram Flow ±1. Algorithms in the Overall Flow Programming or Clear Algorithm ±2. The Programming Algorithm in the Overall FlowPreliminary ±3. Programming or Clear Algorithm Flow Step Action Description Mask the data to program Preliminary Erase Algorithm ±4. Erase Algorithm in the Overall Flow±2. Steps for Applying One Erase Pulse Preliminary ±5. Erase Algorithm Flow Flash-Write Algorithm ±6. Flash-Write Algorithm in the Overall Flow±3. Steps for Applying One Flash-Write Pulse ±7. Flash-Write Algorithm Flow Preliminary Preliminary Assembly Source Listings Program Examples Assembly Source for Algorithms Header File for Constants and Variables, SVAR20.HError BASE0BASE+0 BASE1Constants D5KD7K DloopClear Algorithm, SCLR20.ASM SegstSegend ProtectGclr PROTECT,SEGST,SEGEND DELAY,REGS,ARRAY Splk #0,ERRORAR0 AR1Exit Splk #1,ERROR Sacl FlstLacl Fladrs NewrowActivate Write BIT Tblw SPAD1 Execute Command LAR SET Delay Call DELAY,*,AR6 Wait Stop Write Operation SplkShutdown Write Operation Tblw SPAD1 Execute Command LAR Tblr FldataTblw SPAD1 Execute Command LAR Prgbyte Call SETRDVER0Lacl BASE2 Bcnd PBDONE,EQErase Algorithm, SERA20.ASM Erase Command Word Erase Exebin Command WordInverse Erase Command Word Flash Write Command WordClrc OVM Sacl FlendCall Setmode XoreraseSplk #STOP,BASE0 Inverase Splk #INVER,BASE0 Call SetmodeBldd Nextivers Lacl BASE1Flash Stop command, and Ffff for Wdata Flash-Write Algorithm, SFLW20.ASM Flws MaxflwBldd #FLST,BASE1 Call Array Access Flash Array Done Call DELAY,*,AR6Bcnd Flwrite SplkLAR AR0,#MAXFLW Cmpr Setmode Call Lacl Tblw LAR Call Call RETProgramming Algorithm, SPGM20.ASM PROTECT,DELAY,REGS,ARRAY AR3AR4 GpgmjSetc Intm Globally Mask ALL Interrupts Splk #0,ERROR Gpgmj SplkMask ALL Interrupts SUB Sacl BASE4Rowdone Lacl Fladrs Bcnd DONE, GTLacl Fladrs Newrow Adjrow NEGShut Down Write Operation Tblw SPAD1 Execute Command LAR SETRDVER0 Call Regs Access Flash RegistersBcnd PBEND,EQ XOR FldataPbend RET Subroutines Used By All Four Algorithms, SUTILS20.ASM OUT SPAD2,FACCESS0 SPAD2,FACCESS1OUT SPAD2,F24XACCS Lacc Flst SUBCallable Interface to Flash Algorithms Gclr SEGST,SEGEND,PROTECTPARMS+1 PARMS+2Lacl Error ErsparamsArstack ArprotectSacl Erscount Call FlwsLAR AR1,SVAR1 1PROTECTPopd *+ Call GpgmjSample Assembly Code to Erase and Reprogram the TMS320F206 Assembly Code for TMS320F206PARMS+1 SUB Memory Block B2 SectionsPsaram DLY PsaramSample C Code to Erase and Reprogram the TMS320F206 Linker Command File for TMS320F206 Sample C Code FLASH0 FLASH1BLKB2 Block B2 DsaramSample Assembly Code to Erase and Reprogram the TMS320F240 Assembly Code for TMS320F240Rticr WdcrCKCR0 CKCR1LDP #DPPF1 PORRST, PLLRST, Illrst SWRST, Wdrst Lacl Syssr Accl = SyssrSacl Syssr LDP #PARMS SplkDaram LDP #PARMS Extram Linker Command File for TMS320F240 Sample Assembly CodeB0PGM Extram 0 /******Delay Subroutine Rev1.003/98 JGC Linker Command File for TMS320F240 Sample C Code Block B2 Dsram B0DATCompute Length Function for Disabling TMS320F240 Watchdog TimerLacl Wdcr Functions for Initializing the TMS320F240 Sacl WdcrPshd SyscrSacl Wdtcr Index Assembly code SERA2x.ASM Described 10 to Margin Role in single program pulse WRITE/ERASE field Described