Cypress CY7C1363C manual Features, Selection Guide Functional Description1, MHz 100 MHz Unit

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CY7C1361C

CY7C1363C

9-Mbit (256K x 36/512K x 18) Flow-Through SRAM

Features

•Supports 100, 133-MHz bus operations

•Supports 100-MHz bus operations (Automotive)

•256K × 36/512K × 18 common I/O

•3.3V –5% and +10% core power supply (VDD)

•2.5V or 3.3V I/O power supply (VDDQ)

•Fast clock-to-output times

— 6.5 ns (133-MHz version)

•Provide high-performance 2-1-1-1 access rate

•User-selectable burst counter supporting Intel→ Pentium→ interleaved or linear burst sequences

•Separate processor and controller address strobes

•Synchronous self-timed write

•Asynchronous output enable

•Available in lead-free 100-Pin TQFP package, lead-free and non lead-free 119-Ball BGA package and 165-Ball FBGA package

•TQFP Available with 3-Chip Enable and 2-Chip Enable

•IEEE 1149.1 JTAG-Compatible Boundary Scan

•“ZZ” Sleep Mode option

Selection Guide

Functional Description[1]

The CY7C1361C/CY7C1363C is a 3.3V, 256K x 36/512K x 18 Synchronous Flow-through SRAMs, respectively designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133-MHz version). A 2-bit on-chip counter captures the first address in a burst and increments the address automatically for the rest of the burst access. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). The synchronous inputs include all addresses, all data inputs, address-pipelining Chip Enable (CE1), depth-expansion Chip Enables (CE2 and CE3[2]), Burst Control inputs (ADSC, ADSP, and ADV), Write Enables (BWx, and BWE), and Global Write (GW). Asynchronous inputs include the Output Enable (OE) and the ZZ pin.

The CY7C1361C/CY7C1363C allows either interleaved or linear burst sequences, selected by the MODE input pin. A HIGH selects an interleaved burst sequence, while a LOW selects a linear burst sequence. Burst accesses can be initiated with the Processor Address Strobe (ADSP) or the cache Controller Address Strobe (ADSC) inputs. Address advancement is controlled by the Address Advancement (ADV) input.

Addresses and chip enables are registered at rising edge of clock when either Address Strobe Processor (ADSP) or Address Strobe Controller (ADSC) are active. Subsequent burst addresses can be internally generated as controlled by the Advance pin (ADV).

The CY7C1361C/CY7C1363C operates from a +3.3V core power supply while all outputs may operate with either a +2.5 or +3.3V supply. All inputs and outputs are JEDEC-standard JESD8-5-compatible.

 

 

133 MHz

100 MHz

Unit

Maximum Access Time

 

6.5

8.5

ns

 

 

 

 

 

Maximum Operating Current

 

250

180

mA

 

 

 

 

 

Maximum CMOS Standby Current

Comm/Ind’l

40

40

mA

 

 

 

 

 

 

Automotive

 

60

mA

 

 

 

 

 

Notes:

1.For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.

2.CE3 is for A version of TQFP (3 Chip Enable Option) and 165 FBGA package only. 119 BGA is offered only in 2 Chip Enable.

Cypress Semiconductor Corporation

•

198 Champion Court • San Jose, CA 95134-1709

•

408-943-2600

Document #: 38-05541 Rev. *F

 

Revised September 14, 2006

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Contents Selection Guide Functional Description1 Features133 MHz 100 MHz Unit Cypress Semiconductor CorporationLogic Block Diagram CY7C1363C 512K x Logic Block Diagram CY7C1361C 256K xCY7C1361C 256K x Pin Configurations Pin Tqfp Pinout 3 Chip Enables a versionCY7C1363C 512K x CY7C1363C Pin Configurations Pin Tqfp Pinout 2 Chip Enables AJ VersionPin Configurations Ball BGA Pinout 2 Chip Enables with Jtag BWE Adsc ADV Pin Configurations Ball Fbga Pinout 3 Chip EnableCLK DQP BPower supply for the I/O circuitry Power supply inputs to the core of the deviceName Description Ground for the core of the device Pin DefinitionsGround for the I/O circuitry Functional Overview Interleaved Burst Address Table Mode = Floating or VDDBurst Sequences AddressParameter Description Test Conditions Min Max Unit ZZ Mode Electrical CharacteristicsAddress Cycle Description Used Truth Table for Read/Write3 Partial Truth Table for Read/Write3Function CY7C1361C Function CY7C1363CTAP Controller State Diagram TAP Controller Block DiagramIeee 1149.1 Serial Boundary Scan Jtag TAP Instruction Set Bypass RegisterParameter Min Max Unit Clock TAP TimingOutput Times Set-up Times3V TAP AC Test Conditions TAP DC Electrical Characteristics And Operating Conditions5V TAP AC Test Conditions Identification Register DefinitionsIdentification Codes Scan Register SizesRegister Name Bit Size x Instruction Code DescriptionCY7C1363C 512K x Bit # Ball ID Signal Name CY7C1361C 256K x Bit # Ball ID SignalBall BGA Boundary Scan Order NameBall Fbga Boundary Scan Order CY7C1361C 256K x Bit # Ball ID Signal NameMaximum Ratings Electrical Characteristics Over the Operating Range 13Operating Range Ambient RangeThermal Resistance Capacitance15AC Test Loads and Waveforms 3V I/O Test Load133 100 Parameter Description Unit Min Max Switching Characteristics Over the Operating Range20Read Cycle Timing22 Timing DiagramsAdsc Address GW, BWE,BWXDON’T Care Write Cycle Timing22Burst Read DON’T Care Undefined Read/Write Cycle Timing22, 24ZZ Mode Timing26 Chip Enable CY7C1363C-133AXI CY7C1361C-133AJXI Chip Enable CY7C1363C-133AXC CY7C1361C-133AJXCOrdering Information CY7C1361C-133AXCChip Enable CY7C1363C-100AXI CY7C1361C-100AJXI Chip Enable CY7C1363C-100AXC CY7C1361C-100AJXCCY7C1361C-100AXC CY7C1361C-100AXEPin Tqfp 14 x 20 x 1.4 mm Package DiagramsBall BGA 14 x 22 x 2.4 mm Soldernotespad Type NON-SOLDER Mask Defined Nsmd Document History Issue Date Orig. Description of Change
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