Cypress CY7C1361C-100AXC, Chip Enable CY7C1363C-100AXC CY7C1361C-100AJXC, CY7C1361C-100AXE

Page 27

CY7C1361C

CY7C1363C

Ordering Information (continued)

Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or

visit www.cypress.com for actual products offered.

Speed

Ordering Code

Package

Part and Package Type

Operating

(MHz)

Diagram

Range

 

 

 

 

 

100

CY7C1361C-100AXC

51-85050

100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free

Commercial

 

 

 

(3 Chip Enable)

 

 

CY7C1363C-100AXC

 

 

 

 

 

 

 

 

 

 

 

 

CY7C1361C-100AJXC

51-85050

100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free

 

 

 

 

(2 Chip Enable)

 

 

CY7C1363C-100AJXC

 

 

 

 

 

 

 

 

 

 

 

 

CY7C1361C-100BGC

51-85115

119-ball Ball Grid Array (14 x 22 x 2.4 mm)

 

 

 

 

 

 

 

CY7C1363C-100BGC

 

 

 

 

 

 

 

 

 

CY7C1361C-100BGXC

51-85115

119-ball Ball Grid Array (14 x 22 x 2.4 mm) Lead-Free

 

 

 

 

 

 

 

CY7C1363C-100BGXC

 

 

 

 

 

 

 

 

 

CY7C1361C-100BZC

51-85180

165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)

 

 

 

 

 

 

 

CY7C1363C-100BZC

 

 

 

 

 

 

 

 

 

CY7C1361C-100BZXC

51-85180

165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) Lead-Free

 

 

 

 

 

 

 

CY7C1363C-100BZXC

 

 

 

 

 

 

 

 

 

CY7C1361C-100AXI

51-85050

100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free

lndustrial

 

 

 

(3 Chip Enable)

 

 

CY7C1363C-100AXI

 

 

 

 

 

 

 

 

 

 

 

 

CY7C1361C-100AJXI

51-85050

100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free

 

 

 

 

(2 Chip Enable)

 

 

CY7C1363C-100AJXI

 

 

 

 

 

 

 

 

 

 

 

 

CY7C1361C-100BGI

51-85115

119-ball Ball Grid Array (14 x 22 x 2.4 mm)

 

 

 

 

 

 

 

CY7C1363C-100BGI

 

 

 

 

 

 

 

 

 

CY7C1361C-100BGXI

51-85115

119-ball Ball Grid Array (14 x 22 x 2.4 mm) Lead-Free

 

 

 

 

 

 

 

CY7C1363C-100BGXI

 

 

 

 

 

 

 

 

 

CY7C1361C -100BZI

51-85180

165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)

 

 

 

 

 

 

 

CY7C1363C-100BZI

 

 

 

 

 

 

 

 

 

CY7C1361C-100BZXI

51-85180

165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) Lead-Free

 

 

 

 

 

 

 

CY7C1363C-100BZXI

 

 

 

 

 

 

 

 

100

CY7C1361C-100AXE

51-85050

100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free

Automotive

 

 

 

 

 

Document #: 38-05541 Rev. *F

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Contents Cypress Semiconductor Corporation FeaturesSelection Guide Functional Description1 133 MHz 100 MHz UnitLogic Block Diagram CY7C1363C 512K x Logic Block Diagram CY7C1361C 256K xPin Configurations Pin Tqfp Pinout 3 Chip Enables a version CY7C1361C 256K xCY7C1363C 512K x CY7C1363C Pin Configurations Pin Tqfp Pinout 2 Chip Enables AJ VersionPin Configurations Ball BGA Pinout 2 Chip Enables with Jtag DQP B Pin Configurations Ball Fbga Pinout 3 Chip EnableBWE Adsc ADV CLKPower supply inputs to the core of the device Power supply for the I/O circuitryName Description Pin Definitions Ground for the core of the deviceGround for the I/O circuitry Address Interleaved Burst Address Table Mode = Floating or VDDFunctional Overview Burst SequencesZZ Mode Electrical Characteristics Parameter Description Test Conditions Min Max UnitAddress Cycle Description Used Function CY7C1363C Partial Truth Table for Read/Write3Truth Table for Read/Write3 Function CY7C1361CTAP Controller Block Diagram TAP Controller State DiagramIeee 1149.1 Serial Boundary Scan Jtag TAP Instruction Set Bypass RegisterSet-up Times TAP TimingParameter Min Max Unit Clock Output TimesIdentification Register Definitions TAP DC Electrical Characteristics And Operating Conditions3V TAP AC Test Conditions 5V TAP AC Test ConditionsInstruction Code Description Scan Register SizesIdentification Codes Register Name Bit Size xName CY7C1361C 256K x Bit # Ball ID SignalCY7C1363C 512K x Bit # Ball ID Signal Name Ball BGA Boundary Scan OrderBall Fbga Boundary Scan Order CY7C1361C 256K x Bit # Ball ID Signal NameAmbient Range Electrical Characteristics Over the Operating Range 13Maximum Ratings Operating Range3V I/O Test Load Capacitance15Thermal Resistance AC Test Loads and Waveforms133 100 Parameter Description Unit Min Max Switching Characteristics Over the Operating Range20GW, BWE,BWX Timing DiagramsRead Cycle Timing22 Adsc AddressDON’T Care Write Cycle Timing22Burst Read DON’T Care Undefined Read/Write Cycle Timing22, 24ZZ Mode Timing26 CY7C1361C-133AXC Chip Enable CY7C1363C-133AXC CY7C1361C-133AJXCChip Enable CY7C1363C-133AXI CY7C1361C-133AJXI Ordering InformationCY7C1361C-100AXE Chip Enable CY7C1363C-100AXC CY7C1361C-100AJXCChip Enable CY7C1363C-100AXI CY7C1361C-100AJXI CY7C1361C-100AXCPin Tqfp 14 x 20 x 1.4 mm Package DiagramsBall BGA 14 x 22 x 2.4 mm Soldernotespad Type NON-SOLDER Mask Defined Nsmd Document History Issue Date Orig. Description of Change
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