Cypress CY7C1361C, CY7C1363C manual Pin Definitions, Ground for the core of the device

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				CY7C1361C
				CY7C1363C



Pin Definitions (continued)

Name	I/O			Description

VSS	Ground			Ground for the core of the device.
VSSQ	I/O Ground			Ground for the I/O circuitry.
TDO	JTAG serial output			Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. If the
	Synchronous			JTAG feature is not being utilized, this pin should be left unconnected. This pin is not
				available on TQFP packages.
TDI	JTAG serial input			Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG
	Synchronous			feature is not being utilized, this pin can be left floating or connected to VDD through a pull
				up resistor. This pin is not available on TQFP packages.
TMS	JTAG serial input			Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG
	Synchronous			feature is not being utilized, this pin can be disconnected or connected to VDD. This pin
				is not available on TQFP packages.
TCK	JTAG-			Clock input to the JTAG circuitry. If the JTAG feature is not being utilized, this pin must
	Clock			be connected to VSS. This pin is not available on TQFP packages.
NC	–			No Connects. Not internally connected to the die. 18M, 36M, 72M, 144M, 288M, 576M
				and 1G are address expansion pins and are not internally connected to the die.
VSS/DNU	Ground/DNU			This pin can be connected to Ground or should be left floating.

Document #: 38-05541 Rev. *F

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Contents Features Selection Guide Functional Description1133 MHz 100 MHz Unit Cypress Semiconductor CorporationLogic Block Diagram CY7C1361C 256K x Logic Block Diagram CY7C1363C 512K xCY7C1363C 512K x Pin Configurations Pin Tqfp Pinout 3 Chip Enables a versionCY7C1361C 256K x Pin Configurations Pin Tqfp Pinout 2 Chip Enables AJ Version CY7C1363CPin Configurations Ball BGA Pinout 2 Chip Enables with Jtag Pin Configurations Ball Fbga Pinout 3 Chip Enable BWE Adsc ADVCLK DQP BName Description Power supply inputs to the core of the devicePower supply for the I/O circuitry Ground for the I/O circuitry Pin DefinitionsGround for the core of the device Interleaved Burst Address Table Mode = Floating or VDD Functional OverviewBurst Sequences AddressAddress Cycle Description Used ZZ Mode Electrical CharacteristicsParameter Description Test Conditions Min Max Unit Partial Truth Table for Read/Write3 Truth Table for Read/Write3Function CY7C1361C Function CY7C1363CIeee 1149.1 Serial Boundary Scan Jtag TAP Controller Block DiagramTAP Controller State Diagram Bypass Register TAP Instruction SetTAP Timing Parameter Min Max Unit ClockOutput Times Set-up TimesTAP DC Electrical Characteristics And Operating Conditions 3V TAP AC Test Conditions5V TAP AC Test Conditions Identification Register DefinitionsScan Register Sizes Identification CodesRegister Name Bit Size x Instruction Code DescriptionCY7C1361C 256K x Bit # Ball ID Signal CY7C1363C 512K x Bit # Ball ID Signal NameBall BGA Boundary Scan Order NameCY7C1361C 256K x Bit # Ball ID Signal Name Ball Fbga Boundary Scan OrderElectrical Characteristics Over the Operating Range 13 Maximum RatingsOperating Range Ambient RangeCapacitance15 Thermal ResistanceAC Test Loads and Waveforms 3V I/O Test LoadSwitching Characteristics Over the Operating Range20 133 100 Parameter Description Unit Min MaxTiming Diagrams Read Cycle Timing22Adsc Address GW, BWE,BWXWrite Cycle Timing22 DON’T CareRead/Write Cycle Timing22, 24 Burst Read DON’T Care UndefinedZZ Mode Timing26 Chip Enable CY7C1363C-133AXC CY7C1361C-133AJXC Chip Enable CY7C1363C-133AXI CY7C1361C-133AJXIOrdering Information CY7C1361C-133AXCChip Enable CY7C1363C-100AXC CY7C1361C-100AJXC Chip Enable CY7C1363C-100AXI CY7C1361C-100AJXICY7C1361C-100AXC CY7C1361C-100AXEPackage Diagrams Pin Tqfp 14 x 20 x 1.4 mmBall BGA 14 x 22 x 2.4 mm Soldernotespad Type NON-SOLDER Mask Defined Nsmd Issue Date Orig. Description of Change Document History