Cypress CY7C1361C, CY7C1363C manual Capacitance15, Thermal Resistance, AC Test Loads and Waveforms

Page 20

CY7C1361C

CY7C1363C

Capacitance[15]

Parameter

Description

Test Conditions

100 TQFP

119 BGA

165 FBGA

Unit

Max.

Max.

Max.

 

 

 

 

 

 

 

CIN

Input Capacitance

TA = 25°C, f = 1 MHz,

5

5

5

pF

 

 

VDD = 3.3V

 

 

 

 

CCLK

Clock Input Capacitance

5

5

5

pF

 

 

VDDQ = 2.5V

 

 

 

 

CI/O

Input/Output Capacitance

5

7

7

pF

 

Thermal Resistance[15]

 

 

 

 

 

Parameter

Description

Test Conditions

100 TQFP

119 BGA

165 FBGA

Unit

Package

Package

Package

 

 

 

 

 

 

 

ΘJA

Thermal Resistance

Test conditions follow standard

29.41

34.1

16.8

°C/W

 

(Junction to Ambient)

test methods and procedures

 

 

 

 

 

 

for measuring thermal

 

 

 

 

ΘJC

Thermal Resistance

6.31

14.0

3.0

°C/W

impedance, per EIA/JESD51

 

(Junction to Case)

 

 

 

 

 

AC Test Loads and Waveforms

3.3V I/O Test Load

 

 

 

 

 

 

 

 

 

 

R = 317

OUTPUT

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

3.3V

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Z0

= 50

 

 

 

 

 

 

OUTPUT

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

RL

= 50

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

5 pF

 

 

 

 

 

 

 

 

 

 

 

 

 

R = 351

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

INCLUDING

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VT = 1.5V

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

JIG AND

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

(a)

 

SCOPE

 

 

 

 

 

(b)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

2.5V I/O Test Load

 

 

 

 

 

 

 

 

 

 

R = 1667

OUTPUT

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

2.5V

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Z0

= 50

 

 

 

 

 

 

OUTPUT

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

RL

= 50

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

5 pF

 

 

 

 

 

 

 

 

 

 

 

 

 

R = 1538

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VT = 1.25V

INCLUDING

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

JIG AND

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

(a)

 

 

 

 

 

 

 

(b)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SCOPE

 

 

 

 

 

 

 

Note:

15. Tested initially and after any design or process change that may affect these parameters.

VDDQ

 

 

 

 

ALL INPUT PULSES

 

 

 

 

 

 

 

90%

 

 

10%

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

GND

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1 ns

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

(c)

 

 

 

 

 

 

 

 

 

 

VDDQ

 

 

 

 

ALL INPUT PULSES

 

 

 

 

 

 

 

90%

 

 

10%

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

GND

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1 ns

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

(c)

90%

10%

1 ns

90%

10%

1 ns

Document #: 38-05541 Rev. *F

Page 20 of 31

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Contents Features Selection Guide Functional Description1133 MHz 100 MHz Unit Cypress Semiconductor CorporationLogic Block Diagram CY7C1361C 256K x Logic Block Diagram CY7C1363C 512K xCY7C1363C 512K x Pin Configurations Pin Tqfp Pinout 3 Chip Enables a versionCY7C1361C 256K x Pin Configurations Pin Tqfp Pinout 2 Chip Enables AJ Version CY7C1363CPin Configurations Ball BGA Pinout 2 Chip Enables with Jtag Pin Configurations Ball Fbga Pinout 3 Chip Enable BWE Adsc ADVCLK DQP BName Description Power supply inputs to the core of the devicePower supply for the I/O circuitry Ground for the I/O circuitry Pin DefinitionsGround for the core of the device Interleaved Burst Address Table Mode = Floating or VDD Functional OverviewBurst Sequences AddressAddress Cycle Description Used ZZ Mode Electrical CharacteristicsParameter Description Test Conditions Min Max Unit Partial Truth Table for Read/Write3 Truth Table for Read/Write3Function CY7C1361C Function CY7C1363CIeee 1149.1 Serial Boundary Scan Jtag TAP Controller Block DiagramTAP Controller State Diagram Bypass Register TAP Instruction SetTAP Timing Parameter Min Max Unit ClockOutput Times Set-up TimesTAP DC Electrical Characteristics And Operating Conditions 3V TAP AC Test Conditions5V TAP AC Test Conditions Identification Register DefinitionsScan Register Sizes Identification CodesRegister Name Bit Size x Instruction Code DescriptionCY7C1361C 256K x Bit # Ball ID Signal CY7C1363C 512K x Bit # Ball ID Signal NameBall BGA Boundary Scan Order NameCY7C1361C 256K x Bit # Ball ID Signal Name Ball Fbga Boundary Scan OrderElectrical Characteristics Over the Operating Range 13 Maximum RatingsOperating Range Ambient RangeCapacitance15 Thermal ResistanceAC Test Loads and Waveforms 3V I/O Test LoadSwitching Characteristics Over the Operating Range20 133 100 Parameter Description Unit Min MaxTiming Diagrams Read Cycle Timing22Adsc Address GW, BWE,BWXWrite Cycle Timing22 DON’T CareRead/Write Cycle Timing22, 24 Burst Read DON’T Care UndefinedZZ Mode Timing26 Chip Enable CY7C1363C-133AXC CY7C1361C-133AJXC Chip Enable CY7C1363C-133AXI CY7C1361C-133AJXIOrdering Information CY7C1361C-133AXCChip Enable CY7C1363C-100AXC CY7C1361C-100AJXC Chip Enable CY7C1363C-100AXI CY7C1361C-100AJXICY7C1361C-100AXC CY7C1361C-100AXEPackage Diagrams Pin Tqfp 14 x 20 x 1.4 mmBall BGA 14 x 22 x 2.4 mm Soldernotespad Type NON-SOLDER Mask Defined Nsmd Issue Date Orig. Description of Change Document History