Cypress manual Logic Block Diagram CY7C1361C 256K x, Logic Block Diagram CY7C1363C 512K x

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						CY7C1361C
						CY7C1363C
Logic Block Diagram – CY7C1361C (256K x 36)
A0, A1, A	ADDRESS
A0, A1, A	REGISTER
	REGISTER
MODE			A[1:0]
MODE
ADV		BURST Q1
CLK	COUNTER
	AND LOGIC
	CLR	Q0
	CLR
ADSC
ADSP
	DQD, DQPD		DQD, DQPD
BWD	DQD, DQPD		BYTE
BWD	BYTE		BYTE
	BYTE		WRITE REGISTER
	WRITE REGISTER		WRITE REGISTER
	WRITE REGISTER
	DQC, DQPC		DQC, DQPC
BWC	DQC, DQPC		BYTE
BWC	BYTE		BYTE
	BYTE		WRITE REGISTER
	WRITE REGISTER		WRITE REGISTER	MEMORY		OUTPUT	DQs
	WRITE REGISTER			MEMORY	SENSE	OUTPUT	DQs
				ARRAY	SENSE	BUFFERS	DQPA
			DQB, DQPB	ARRAY	AMPS	BUFFERS	DQPA
	DQB, DQPB		DQB, DQPB		AMPS		DQPB
BWB	DQB, DQPB		BYTE				DQPB
	BYTE		BYTE				DQPC
			WRITE REGISTER

	WRITE REGISTER						DQPD
	WRITE REGISTER						DQPD
			DQA, DQPA
BWA	DQA, DQPA		BYTE
BWA	BYTE		WRITE REGISTER
BWE	BYTE		WRITE REGISTER
BWE	WRITE REGISTER
	WRITE REGISTER
GW						INPUT
CE1	ENABLE					REGISTERS
	ENABLE
	REGISTER
CE2	REGISTER
CE2
CE3
OE
ZZ	SLEEP
ZZ	CONTROL
	CONTROL
Logic Block Diagram – CY7C1363C (512K x 18)
A0,A1,A	ADDRESS
A0,A1,A	REGISTER
	REGISTER
MODE			A[1:0]
MODE
ADV		BURST	Q1
CLK		COUNTER AND
		LOGIC
		CLR	Q0
ADSC
ADSP
	DQB,DQPB		DQB,DQPB
	DQB,DQPB		WRITE DRIVER
BWB	WRITE REGISTER		WRITE DRIVER	MEMORY		OUTPUT	DQs
BWB				MEMORY	SENSE	OUTPUT
				ARRAY	SENSE	BUFFERS
				ARRAY	AMPS		DQPA
					AMPS		DQPA
	DQA,DQPA		DQA,DQPA				DQPB
BWA	DQA,DQPA		WRITE DRIVER
	WRITE REGISTER		WRITE DRIVER
	WRITE REGISTER
BWE						INPUT
GW						INPUT
GW	ENABLE					REGISTERS
CE1	ENABLE					REGISTERS
CE1	REGISTER
CE2	REGISTER
CE2
CE3
OE
ZZ	SLEEP
	CONTROL
Document #: 38-05541 Rev. *F						Page 2 of 31

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Contents 133 MHz 100 MHz Unit FeaturesSelection Guide Functional Description1 Cypress Semiconductor CorporationLogic Block Diagram CY7C1361C 256K x Logic Block Diagram CY7C1363C 512K xCY7C1363C 512K x Pin Configurations Pin Tqfp Pinout 3 Chip Enables a versionCY7C1361C 256K x Pin Configurations Pin Tqfp Pinout 2 Chip Enables AJ Version CY7C1363CPin Configurations Ball BGA Pinout 2 Chip Enables with Jtag CLK Pin Configurations Ball Fbga Pinout 3 Chip EnableBWE Adsc ADV DQP BName Description Power supply inputs to the core of the devicePower supply for the I/O circuitry Ground for the I/O circuitry Pin DefinitionsGround for the core of the device Burst Sequences Interleaved Burst Address Table Mode = Floating or VDDFunctional Overview AddressAddress Cycle Description Used ZZ Mode Electrical CharacteristicsParameter Description Test Conditions Min Max Unit Function CY7C1361C Partial Truth Table for Read/Write3Truth Table for Read/Write3 Function CY7C1363CIeee 1149.1 Serial Boundary Scan Jtag TAP Controller Block DiagramTAP Controller State Diagram Bypass Register TAP Instruction SetOutput Times TAP TimingParameter Min Max Unit Clock Set-up Times5V TAP AC Test Conditions TAP DC Electrical Characteristics And Operating Conditions3V TAP AC Test Conditions Identification Register DefinitionsRegister Name Bit Size x Scan Register SizesIdentification Codes Instruction Code DescriptionBall BGA Boundary Scan Order CY7C1361C 256K x Bit # Ball ID SignalCY7C1363C 512K x Bit # Ball ID Signal Name NameCY7C1361C 256K x Bit # Ball ID Signal Name Ball Fbga Boundary Scan OrderOperating Range Electrical Characteristics Over the Operating Range 13Maximum Ratings Ambient RangeAC Test Loads and Waveforms Capacitance15Thermal Resistance 3V I/O Test LoadSwitching Characteristics Over the Operating Range20 133 100 Parameter Description Unit Min MaxAdsc Address Timing DiagramsRead Cycle Timing22 GW, BWE,BWXWrite Cycle Timing22 DON’T CareRead/Write Cycle Timing22, 24 Burst Read DON’T Care UndefinedZZ Mode Timing26 Ordering Information Chip Enable CY7C1363C-133AXC CY7C1361C-133AJXCChip Enable CY7C1363C-133AXI CY7C1361C-133AJXI CY7C1361C-133AXCCY7C1361C-100AXC Chip Enable CY7C1363C-100AXC CY7C1361C-100AJXCChip Enable CY7C1363C-100AXI CY7C1361C-100AJXI CY7C1361C-100AXEPackage Diagrams Pin Tqfp 14 x 20 x 1.4 mmBall BGA 14 x 22 x 2.4 mm Soldernotespad Type NON-SOLDER Mask Defined Nsmd Issue Date Orig. Description of Change Document History