Cypress CY7C1363C, CY7C1361C manual 3V TAP AC Test Conditions, 5V TAP AC Test Conditions

Page 15

CY7C1361C

CY7C1363C

3.3V TAP AC Test Conditions

Input pulse levels

VSS to 3.3V

Input rise and fall times

1 ns

Input timing reference levels

1.5V

Output reference levels

1.5V

Test load termination supply voltage

1.5V

2.5V TAP AC Test Conditions

Input pulse levels

VSS to 2.5V

Input rise and fall time

1 ns

Input timing reference levels

1.25V

Output reference levels

1.25V

Test load termination supply voltage

1.25V

3.3V TAP AC Output Load Equivalent

2.5V TAP AC Output Load Equivalent

 

 

 

 

 

 

 

 

1.5V

 

 

 

 

 

 

 

1.25V

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

50Ω

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

50Ω

 

TDO

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TDO

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ZO= 50Ω

 

 

 

 

 

 

 

20pF

 

 

 

 

ZO= 50Ω

 

 

 

 

 

 

 

 

 

20pF

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TAP DC Electrical Characteristics And Operating Conditions

 

 

 

 

 

 

 

 

 

 

 

(0°C < TA < +70°C; VDD = 3.3V ±0.165V unless otherwise noted)[11]

 

 

 

 

 

 

 

 

 

 

 

Parameter

 

 

 

Description

 

 

 

 

 

 

 

 

Description

 

 

Conditions

 

Min.

 

Max.

Unit

VOH1

 

Output HIGH Voltage

 

 

 

 

 

 

 

 

IOH = –4.0 mA

 

VDDQ = 3.3V

 

2.4

 

 

 

 

 

V

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

IOH = –1.0 mA

 

VDDQ = 2.5V

 

2.0

 

 

 

 

 

V

VOH2

 

Output HIGH Voltage

 

 

 

 

 

 

 

 

IOH = –100 µA

 

VDDQ = 3.3V

 

2.9

 

 

 

 

 

V

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VDDQ = 2.5V

 

2.1

 

 

 

 

 

V

VOL1

 

Output LOW Voltage

 

 

 

 

 

 

 

 

IOL = 8.0 mA

 

VDDQ = 3.3V

 

 

 

 

 

 

 

 

 

0.4

V

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

IOL = 8.0 mA

 

VDDQ = 2.5V

 

 

 

 

 

 

 

 

 

0.4

V

VOL2

 

Output LOW Voltage

 

 

 

 

 

 

 

 

IOL = 100 µA

 

VDDQ = 3.3V

 

 

 

 

 

 

 

 

 

0.2

V

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VDDQ = 2.5V

 

 

 

 

 

 

 

 

 

0.2

V

VIH

 

Input HIGH Voltage

 

 

 

 

 

 

 

 

 

 

VDDQ = 3.3V

 

2.0

 

 

 

 

VDD + 0.3

V

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VDDQ = 2.5V

 

1.7

 

 

 

 

VDD + 0.3

V

VIL

 

Input LOW Voltage

 

 

 

 

 

 

 

 

 

 

VDDQ = 3.3V

 

–0.5

 

0.7

V

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VDDQ = 2.5V

 

–0.3

 

0.7

V

IX

 

Input Load Current

 

 

 

 

 

 

 

 

GND < VIN < VDDQ

 

 

 

 

 

 

 

–5

 

5

µA

Identification Register Definitions

Instruction Field

CY7C1361C

CY7C1363C

Description

(256K x36)

(512K x18)

 

 

 

 

Revision Number (31:29)

000

000

Describes the version number.

 

 

 

 

Device Depth (28:24)[12]

01011

01011

Reserved for Internal Use

Device Width (23:18) 119-BGA

101001

101001

Defines memory type and architecture

 

 

 

 

Device Width (23:18) 165-FBGA

000001

000001

Defines memory type and architecture

 

 

 

 

Cypress Device ID (17:12)

100110

010110

Defines width and density

 

 

 

 

Cypress JEDEC ID Code (11:1)

00000110100

00000110100

Allows unique identification of SRAM vendor.

 

 

 

 

ID Register Presence Indicator (0)

1

1

Indicates the presence of an ID register.

 

 

 

 

Notes:

11.All voltages referenced to VSS (GND).

12.Bit #24 is “1” in the Register Definitions for both 2.5V and 3.3V versions of this device.

Document #: 38-05541 Rev. *F

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Contents Cypress Semiconductor Corporation FeaturesSelection Guide Functional Description1 133 MHz 100 MHz UnitLogic Block Diagram CY7C1363C 512K x Logic Block Diagram CY7C1361C 256K xPin Configurations Pin Tqfp Pinout 3 Chip Enables a version CY7C1361C 256K xCY7C1363C 512K x CY7C1363C Pin Configurations Pin Tqfp Pinout 2 Chip Enables AJ VersionPin Configurations Ball BGA Pinout 2 Chip Enables with Jtag DQP B Pin Configurations Ball Fbga Pinout 3 Chip EnableBWE Adsc ADV CLKPower supply inputs to the core of the device Power supply for the I/O circuitryName Description Pin Definitions Ground for the core of the deviceGround for the I/O circuitry Address Interleaved Burst Address Table Mode = Floating or VDDFunctional Overview Burst SequencesZZ Mode Electrical Characteristics Parameter Description Test Conditions Min Max UnitAddress Cycle Description Used Function CY7C1363C Partial Truth Table for Read/Write3Truth Table for Read/Write3 Function CY7C1361CTAP Controller Block Diagram TAP Controller State DiagramIeee 1149.1 Serial Boundary Scan Jtag TAP Instruction Set Bypass RegisterSet-up Times TAP TimingParameter Min Max Unit Clock Output TimesIdentification Register Definitions TAP DC Electrical Characteristics And Operating Conditions3V TAP AC Test Conditions 5V TAP AC Test ConditionsInstruction Code Description Scan Register SizesIdentification Codes Register Name Bit Size xName CY7C1361C 256K x Bit # Ball ID SignalCY7C1363C 512K x Bit # Ball ID Signal Name Ball BGA Boundary Scan OrderBall Fbga Boundary Scan Order CY7C1361C 256K x Bit # Ball ID Signal NameAmbient Range Electrical Characteristics Over the Operating Range 13Maximum Ratings Operating Range3V I/O Test Load Capacitance15Thermal Resistance AC Test Loads and Waveforms133 100 Parameter Description Unit Min Max Switching Characteristics Over the Operating Range20GW, BWE,BWX Timing DiagramsRead Cycle Timing22 Adsc AddressDON’T Care Write Cycle Timing22Burst Read DON’T Care Undefined Read/Write Cycle Timing22, 24ZZ Mode Timing26 CY7C1361C-133AXC Chip Enable CY7C1363C-133AXC CY7C1361C-133AJXCChip Enable CY7C1363C-133AXI CY7C1361C-133AJXI Ordering InformationCY7C1361C-100AXE Chip Enable CY7C1363C-100AXC CY7C1361C-100AJXCChip Enable CY7C1363C-100AXI CY7C1361C-100AJXI CY7C1361C-100AXCPin Tqfp 14 x 20 x 1.4 mm Package DiagramsBall BGA 14 x 22 x 2.4 mm Soldernotespad Type NON-SOLDER Mask Defined Nsmd Document History Issue Date Orig. Description of Change
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