Cypress CY7C1363C manual Ball BGA Boundary Scan Order, CY7C1361C 256K x Bit # Ball ID Signal, Name

Page 17

CY7C1361C

CY7C1363C

119-Ball BGA Boundary Scan Order

CY7C1361C (256K x 36)

Bit #

ball ID

Signal

Bit #

ball ID

Signal

Name

1

K4

CLK

37

P4

A0

2

H4

38

N4

A1

GW

3

M4

39

R6

A

BWE

4

F4

40

T5

A

OE

5

B4

41

T3

A

ADSC

6

A4

42

R2

A

ADSP

7

G4

ADV

43

R3

MODE

8

C3

A

44

P2

DQPD

9

B3

A

45

P1

DQD

10

D6

DQPB

46

L2

DQD

11

H7

DQB

47

K1

DQD

12

G6

DQB

48

N2

DQD

13

E6

DQB

49

N1

DQD

14

D7

DQB

50

M2

DQD

15

E7

DQB

51

L1

DQD

16

F6

DQB

52

K2

DQD

17

G7

DQB

53

Internal

18

H6

DQB

54

H1

DQC

19

T7

ZZ

55

G2

DQC

20

K7

DQA

56

E2

DQC

21

L6

DQA

57

D1

DQC

22

N6

DQA

58

H2

DQC

23

P7

DQA

59

G1

DQC

24

N7

DQA

60

F2

DQC

25

M6

DQA

61

E1

DQC

26

L7

DQA

62

D2

DQPC

27

K6

DQA

63

C2

A

28

P6

DQPA

64

A2

A

29

T4

A

65

E4

1

CE

30

A3

A

66

B2

CE2

31

C5

A

67

L3

BWD

32

B5

A

68

G3

C

BW

33

A5

A

69

G5

B

BW

34

C6

A

70

L5

A

BW

35

A6

A

71

Internal

36

B6

A

CY7C1363C (512K x 18)

Bit #

ball ID

Signal

Bit #

ball ID

Signal

Name

1

K4

CLK

37

P4

A0

2

H4

38

N4

A1

GW

3

M4

39

R6

A

BWE

4

F4

40

T5

A

OE

5

B4

41

T3

A

ADSC

6

A4

42

R2

A

ADSP

7

G4

43

R3

MODE

ADV

8

C3

A

44

Internal

9

B3

A

45

Internal

10

T2

A

46

Internal

11

Internal

47

Internal

12

Internal

48

P2

DQPB

13

Internal

49

N1

DQB

14

D6

DQPA

50

M2

DQB

15

E7

DQA

51

L1

DQB

16

F6

DQA

52

K2

DQB

17

G7

DQA

53

Internal

18

H6

DQA

54

H1

DQB

19

T7

ZZ

55

G2

DQB

20

K7

DQA

56

E2

DQB

21

L6

DQA

57

D1

DQB

22

N6

DQA

58

Internal

23

P7

DQA

59

Internal

24

Internal

60

Internal

25

Internal

61

Internal

26

Internal

62

Internal

27

Internal

63

C2

A

28

Internal

64

A2

A

29

T6

A

65

E4

1

CE

30

A3

A

66

B2

CE2

31

C5

A

67

Internal

32

B5

A

68

Internal

33

A5

A

69

G3

B

BW

34

C6

A

70

L5

A

BW

35

A6

A

71

Internal

36

B6

A

Document #: 38-05541 Rev. *F

Page 17 of 31

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Image 17

Contents Selection Guide Functional Description1 Features133 MHz 100 MHz Unit Cypress Semiconductor CorporationLogic Block Diagram CY7C1363C 512K x Logic Block Diagram CY7C1361C 256K xCY7C1363C 512K x Pin Configurations Pin Tqfp Pinout 3 Chip Enables a versionCY7C1361C 256K x CY7C1363C Pin Configurations Pin Tqfp Pinout 2 Chip Enables AJ VersionPin Configurations Ball BGA Pinout 2 Chip Enables with Jtag BWE Adsc ADV Pin Configurations Ball Fbga Pinout 3 Chip EnableCLK DQP BName Description Power supply inputs to the core of the devicePower supply for the I/O circuitry Ground for the I/O circuitry Pin DefinitionsGround for the core of the device Functional Overview Interleaved Burst Address Table Mode = Floating or VDDBurst Sequences AddressAddress Cycle Description Used ZZ Mode Electrical CharacteristicsParameter Description Test Conditions Min Max Unit Truth Table for Read/Write3 Partial Truth Table for Read/Write3Function CY7C1361C Function CY7C1363CIeee 1149.1 Serial Boundary Scan Jtag TAP Controller Block DiagramTAP Controller State Diagram TAP Instruction Set Bypass RegisterParameter Min Max Unit Clock TAP TimingOutput Times Set-up Times3V TAP AC Test Conditions TAP DC Electrical Characteristics And Operating Conditions5V TAP AC Test Conditions Identification Register DefinitionsIdentification Codes Scan Register SizesRegister Name Bit Size x Instruction Code DescriptionCY7C1363C 512K x Bit # Ball ID Signal Name CY7C1361C 256K x Bit # Ball ID SignalBall BGA Boundary Scan Order NameBall Fbga Boundary Scan Order CY7C1361C 256K x Bit # Ball ID Signal NameMaximum Ratings Electrical Characteristics Over the Operating Range 13Operating Range Ambient RangeThermal Resistance Capacitance15AC Test Loads and Waveforms 3V I/O Test Load133 100 Parameter Description Unit Min Max Switching Characteristics Over the Operating Range20Read Cycle Timing22 Timing DiagramsAdsc Address GW, BWE,BWXDON’T Care Write Cycle Timing22Burst Read DON’T Care Undefined Read/Write Cycle Timing22, 24ZZ Mode Timing26 Chip Enable CY7C1363C-133AXI CY7C1361C-133AJXI Chip Enable CY7C1363C-133AXC CY7C1361C-133AJXCOrdering Information CY7C1361C-133AXCChip Enable CY7C1363C-100AXI CY7C1361C-100AJXI Chip Enable CY7C1363C-100AXC CY7C1361C-100AJXCCY7C1361C-100AXC CY7C1361C-100AXEPin Tqfp 14 x 20 x 1.4 mm Package DiagramsBall BGA 14 x 22 x 2.4 mm Soldernotespad Type NON-SOLDER Mask Defined Nsmd Document History Issue Date Orig. Description of Change