Cypress Ordering Information, CY7C1361C-133AXC, Chip Enable CY7C1363C-133AXC CY7C1361C-133AJXC

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CY7C1361C

CY7C1363C

Ordering Information

Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or

visit www.cypress.com for actual products offered.

Speed	Ordering Code	Package	Part and Package Type	Operating
(MHz)	Ordering Code	Diagram	Part and Package Type	Range

133	CY7C1361C-133AXC	51-85050	100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free	Commercial
			(3 Chip Enable)
	CY7C1363C-133AXC		(3 Chip Enable)
	CY7C1363C-133AXC

	CY7C1361C-133AJXC	51-85050	100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free
			(2 Chip Enable)
	CY7C1363C-133AJXC		(2 Chip Enable)
	CY7C1363C-133AJXC

	CY7C1361C-133BGC	51-85115	119-ball Ball Grid Array (14 x 22 x 2.4 mm)

	CY7C1363C-133BGC

	CY7C1361C-133BGXC	51-85115	119-ball Ball Grid Array (14 x 22 x 2.4 mm) Lead-Free

	CY7C1363C-133BGXC

	CY7C1361C-133BZC	51-85180	165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)

	CY7C1363C-133BZC

	CY7C1361C-133BZXC	51-85180	165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) Lead-Free

	CY7C1363C-133BZXC

	CY7C1361C-133AXI	51-85050	100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free	lndustrial
			(3 Chip Enable)
	CY7C1363C-133AXI		(3 Chip Enable)
	CY7C1363C-133AXI

	CY7C1361C-133AJXI	51-85050	100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free
			(2 Chip Enable)
	CY7C1363C-133AJXI		(2 Chip Enable)
	CY7C1363C-133AJXI

	CY7C1361C-133BGI	51-85115	119-ball Ball Grid Array (14 x 22 x 2.4 mm)

	CY7C1363C-133BGI

	CY7C1361C-133BGXI	51-85115	119-ball Ball Grid Array (14 x 22 x 2.4 mm) Lead-Free

	CY7C1363C-133BGXI

	CY7C1361C-133BZI	51-85180	165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)

	CY7C1363C-133BZI

	CY7C1361C-133BZXI	51-85180	165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) Lead-Free

	CY7C1363C-133BZXI

Document #: 38-05541 Rev. *F

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Contents 133 MHz 100 MHz Unit FeaturesSelection Guide Functional Description1 Cypress Semiconductor CorporationLogic Block Diagram CY7C1361C 256K x Logic Block Diagram CY7C1363C 512K xCY7C1363C 512K x Pin Configurations Pin Tqfp Pinout 3 Chip Enables a versionCY7C1361C 256K x Pin Configurations Pin Tqfp Pinout 2 Chip Enables AJ Version CY7C1363CPin Configurations Ball BGA Pinout 2 Chip Enables with Jtag CLK Pin Configurations Ball Fbga Pinout 3 Chip EnableBWE Adsc ADV DQP BName Description Power supply inputs to the core of the devicePower supply for the I/O circuitry Ground for the I/O circuitry Pin DefinitionsGround for the core of the device Burst Sequences Interleaved Burst Address Table Mode = Floating or VDDFunctional Overview AddressAddress Cycle Description Used ZZ Mode Electrical CharacteristicsParameter Description Test Conditions Min Max Unit Function CY7C1361C Partial Truth Table for Read/Write3Truth Table for Read/Write3 Function CY7C1363CIeee 1149.1 Serial Boundary Scan Jtag TAP Controller Block DiagramTAP Controller State Diagram Bypass Register TAP Instruction SetOutput Times TAP TimingParameter Min Max Unit Clock Set-up Times5V TAP AC Test Conditions TAP DC Electrical Characteristics And Operating Conditions3V TAP AC Test Conditions Identification Register DefinitionsRegister Name Bit Size x Scan Register SizesIdentification Codes Instruction Code DescriptionBall BGA Boundary Scan Order CY7C1361C 256K x Bit # Ball ID SignalCY7C1363C 512K x Bit # Ball ID Signal Name NameCY7C1361C 256K x Bit # Ball ID Signal Name Ball Fbga Boundary Scan OrderOperating Range Electrical Characteristics Over the Operating Range 13Maximum Ratings Ambient RangeAC Test Loads and Waveforms Capacitance15Thermal Resistance 3V I/O Test LoadSwitching Characteristics Over the Operating Range20 133 100 Parameter Description Unit Min MaxAdsc Address Timing DiagramsRead Cycle Timing22 GW, BWE,BWXWrite Cycle Timing22 DON’T CareRead/Write Cycle Timing22, 24 Burst Read DON’T Care UndefinedZZ Mode Timing26 Ordering Information Chip Enable CY7C1363C-133AXC CY7C1361C-133AJXCChip Enable CY7C1363C-133AXI CY7C1361C-133AJXI CY7C1361C-133AXCCY7C1361C-100AXC Chip Enable CY7C1363C-100AXC CY7C1361C-100AJXCChip Enable CY7C1363C-100AXI CY7C1361C-100AJXI CY7C1361C-100AXEPackage Diagrams Pin Tqfp 14 x 20 x 1.4 mmBall BGA 14 x 22 x 2.4 mm Soldernotespad Type NON-SOLDER Mask Defined Nsmd Issue Date Orig. Description of Change Document History