Cypress CY7C1363C, CY7C1361C manual Write Cycle Timing22, DON’T Care

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CY7C1361C

CY7C1363C

Timing Diagrams (continued)

Write Cycle Timing[22, 23]

CLK

tCYC

tCH tCL

tADS tADH

ADSP

tADS tADH

ADSC

tAS tAH

ADDRESS A1 A2

Byte write signals are ignored for first cycle when

ADSP initiates burst

BWE,

BWX

t t

WES WEH

ADSC extends burst

tADS tADH

tWES tWEH

tCES tCEH

tADVS tADVH

ADV

Data in (D)

High-Z

Data Out (Q)

tOEHZ

tDS t DH

D(A1)

ADV suspends burst

D(A2)

D(A2 + 1)

D(A2 + 2)

D(A2 + 3)

D(A3)

D(A3 + 1)

D(A3 + 2)

BURST READ Single WRITE

BURST WRITE

Extended BURST WRITE

DON’T CARE

UNDEFINED

Note:

23. Full width write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BWX LOW.

Document #: 38-05541 Rev. *F

Page 23 of 31

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Contents Cypress Semiconductor Corporation FeaturesSelection Guide Functional Description1 133 MHz 100 MHz UnitLogic Block Diagram CY7C1363C 512K x Logic Block Diagram CY7C1361C 256K xCY7C1363C 512K x Pin Configurations Pin Tqfp Pinout 3 Chip Enables a versionCY7C1361C 256K x CY7C1363C Pin Configurations Pin Tqfp Pinout 2 Chip Enables AJ VersionPin Configurations Ball BGA Pinout 2 Chip Enables with Jtag DQP B Pin Configurations Ball Fbga Pinout 3 Chip EnableBWE Adsc ADV CLKName Description Power supply inputs to the core of the devicePower supply for the I/O circuitry Ground for the I/O circuitry Pin DefinitionsGround for the core of the device Address Interleaved Burst Address Table Mode = Floating or VDDFunctional Overview Burst SequencesAddress Cycle Description Used ZZ Mode Electrical CharacteristicsParameter Description Test Conditions Min Max Unit Function CY7C1363C Partial Truth Table for Read/Write3Truth Table for Read/Write3 Function CY7C1361CIeee 1149.1 Serial Boundary Scan Jtag TAP Controller Block DiagramTAP Controller State Diagram TAP Instruction Set Bypass RegisterSet-up Times TAP TimingParameter Min Max Unit Clock Output TimesIdentification Register Definitions TAP DC Electrical Characteristics And Operating Conditions3V TAP AC Test Conditions 5V TAP AC Test ConditionsInstruction Code Description Scan Register SizesIdentification Codes Register Name Bit Size xName CY7C1361C 256K x Bit # Ball ID SignalCY7C1363C 512K x Bit # Ball ID Signal Name Ball BGA Boundary Scan OrderBall Fbga Boundary Scan Order CY7C1361C 256K x Bit # Ball ID Signal NameAmbient Range Electrical Characteristics Over the Operating Range 13Maximum Ratings Operating Range3V I/O Test Load Capacitance15Thermal Resistance AC Test Loads and Waveforms133 100 Parameter Description Unit Min Max Switching Characteristics Over the Operating Range20GW, BWE,BWX Timing DiagramsRead Cycle Timing22 Adsc AddressDON’T Care Write Cycle Timing22Burst Read DON’T Care Undefined Read/Write Cycle Timing22, 24ZZ Mode Timing26 CY7C1361C-133AXC Chip Enable CY7C1363C-133AXC CY7C1361C-133AJXCChip Enable CY7C1363C-133AXI CY7C1361C-133AJXI Ordering InformationCY7C1361C-100AXE Chip Enable CY7C1363C-100AXC CY7C1361C-100AJXCChip Enable CY7C1363C-100AXI CY7C1361C-100AJXI CY7C1361C-100AXCPin Tqfp 14 x 20 x 1.4 mm Package DiagramsBall BGA 14 x 22 x 2.4 mm Soldernotespad Type NON-SOLDER Mask Defined Nsmd Document History Issue Date Orig. Description of Change