Cypress CY7C1363C, CY7C1361C manual Maximum Ratings, Operating Range, Ambient Range

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CY7C1361C

CY7C1363C

Maximum Ratings

(Above which the useful life may be impaired. For user guide- lines, not tested.)

Storage Temperature

–65°C to + 150°C

Current into Outputs (LOW)

20 mA

Static Discharge Voltage

>2001V

(per MIL-STD-883, Method 3015)

 

Latch-up Current

>200 mA

Ambient Temperature with

 

 

Power Applied

–55°C to + 125°C

Supply Voltage on VDD Relative to GND

–0.5V to + 4.6V

Supply Voltage on VDDQ Relative to GND

–0.5V to + VDD

DC Voltage Applied to Outputs

 

 

in tri-state

–0.5V to VDDQ + 0.5V

DC Input Voltage

–0.5V to VDD + 0.5V

Operating Range

 

Ambient

 

 

Range

Temperature

VDD

VDDQ

Commercial

0°C to +70°C

3.3V – 5%/+10%

2.5V – 5%

 

 

 

to VDD

Industrial

–40°C to +85°C

 

Automotive

–40°C to +125°C

 

 

Electrical Characteristics Over the Operating Range [13, 14]

Parameter

Description

Test Conditions

Min.

Max.

Unit

VDD

Power Supply Voltage

 

 

3.135

3.6

V

VDDQ

I/O Supply Voltage

for 3.3V I/O

 

3.135

VDD

V

 

 

for 2.5V I/O

 

2.375

2.625

V

 

 

 

 

 

 

 

VOH

Output HIGH Voltage

for 3.3V I/O, IOH = 4.0 mA

 

2.4

 

V

 

 

for 2.5V I/O, IOH = 1.0 mA

 

2.0

 

V

VOL

Output LOW Voltage

for 3.3V I/O, IOL= 8.0 mA

 

 

0.4

V

 

 

for 2.5V I/O, IOL= 1.0 mA

 

 

0.4

V

VIH

Input HIGH Voltage[13]

for 3.3V I/O

 

2.0

VDD + 0.3V

V

 

 

for 2.5V I/O

 

1.7

VDD + 0.3V

V

VIL

Input LOW Voltage[13]

for 3.3V I/O

 

–0.3

0.8

V

 

 

for 2.5V I/O

 

–0.3

0.7

V

 

 

 

 

 

 

 

IX

Input Leakage Current

GND VI VDDQ

 

–5

5

A

 

except ZZ and MODE

 

 

 

 

 

 

Input Current of MODE

Input = VSS

 

–30

 

A

 

 

Input = VDD

 

 

5

A

 

Input Current of ZZ

Input = VSS

 

–5

 

A

 

 

Input = VDD

 

 

30

A

IOZ

Output Leakage Current

GND < VI < VDDQ, Output Disabled

–5

5

A

IDD

VDD Operating Supply

VDD = Max., IOUT = 0 mA,

7.5-ns cycle,133 MHz

 

250

mA

 

Current

f = fMAX = 1/tCYC

 

 

 

 

 

10-ns cycle,100 MHz

 

180

 

ISB1

Automatic CE

Max. VDD, Device Deselected,

All speeds (Comm/Ind’l)

 

110

mA

 

Power-down

VIN> VIH or VIN < VIL, f = fMAX,

 

 

 

 

 

10-ns cycle,100 MHz

 

150

mA

 

Current—TTL Inputs

inputs switching

(Automotive)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ISB2

Automatic CE

Max. VDD, Device Deselected,

All speeds

 

40

mA

 

Power-down

VIN > VDD – 0.3V or VIN < 0.3V,

 

 

 

 

 

Current—CMOS Inputs

f = 0, inputs static

 

 

 

 

ISB3

Automatic CE

Max. VDD, Device Deselected,

All speeds (Comm/Ind’l)

 

100

mA

 

Power-down

VIN > VDDQ – 0.3V or VIN < 0.3V,

 

 

 

 

 

10-ns cycle,100 MHz

 

120

mA

 

Current—CMOS Inputs

f = fMAX, inputs switching

(Automotive)

 

 

 

ISB4

Automatic CE

Max. VDD, Device Deselected,

All speeds (Comm/Ind’l)

 

40

mA

 

Power-down

VIN > VIH or VIN < VIL

 

 

 

 

 

10-ns cycle,100 MHz

 

60

mA

 

Current—TTL Inputs

f = 0, inputs static

(Automotive)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Notes:

13.Overshoot: VIH(AC) < VDD +1.5V (Pulse width less than tCYC/2), undershoot: VIL(AC) > –2V (Pulse width less than tCYC/2).

14.TPower-up: Assumes a linear ramp from 0V to VDD(min.) within 200ms. During this time VIH < VDD and VDDQ < VDD.

Document #: 38-05541 Rev. *F

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Contents Cypress Semiconductor Corporation FeaturesSelection Guide Functional Description1 133 MHz 100 MHz UnitLogic Block Diagram CY7C1363C 512K x Logic Block Diagram CY7C1361C 256K xCY7C1361C 256K x Pin Configurations Pin Tqfp Pinout 3 Chip Enables a versionCY7C1363C 512K x CY7C1363C Pin Configurations Pin Tqfp Pinout 2 Chip Enables AJ VersionPin Configurations Ball BGA Pinout 2 Chip Enables with Jtag DQP B Pin Configurations Ball Fbga Pinout 3 Chip EnableBWE Adsc ADV CLKPower supply for the I/O circuitry Power supply inputs to the core of the deviceName Description Ground for the core of the device Pin DefinitionsGround for the I/O circuitry Address Interleaved Burst Address Table Mode = Floating or VDDFunctional Overview Burst SequencesParameter Description Test Conditions Min Max Unit ZZ Mode Electrical CharacteristicsAddress Cycle Description Used Function CY7C1363C Partial Truth Table for Read/Write3Truth Table for Read/Write3 Function CY7C1361CTAP Controller State Diagram TAP Controller Block DiagramIeee 1149.1 Serial Boundary Scan Jtag TAP Instruction Set Bypass RegisterSet-up Times TAP TimingParameter Min Max Unit Clock Output TimesIdentification Register Definitions TAP DC Electrical Characteristics And Operating Conditions3V TAP AC Test Conditions 5V TAP AC Test ConditionsInstruction Code Description Scan Register SizesIdentification Codes Register Name Bit Size xName CY7C1361C 256K x Bit # Ball ID SignalCY7C1363C 512K x Bit # Ball ID Signal Name Ball BGA Boundary Scan OrderBall Fbga Boundary Scan Order CY7C1361C 256K x Bit # Ball ID Signal NameAmbient Range Electrical Characteristics Over the Operating Range 13Maximum Ratings Operating Range3V I/O Test Load Capacitance15Thermal Resistance AC Test Loads and Waveforms133 100 Parameter Description Unit Min Max Switching Characteristics Over the Operating Range20GW, BWE,BWX Timing DiagramsRead Cycle Timing22 Adsc AddressDON’T Care Write Cycle Timing22Burst Read DON’T Care Undefined Read/Write Cycle Timing22, 24ZZ Mode Timing26 CY7C1361C-133AXC Chip Enable CY7C1363C-133AXC CY7C1361C-133AJXCChip Enable CY7C1363C-133AXI CY7C1361C-133AJXI Ordering InformationCY7C1361C-100AXE Chip Enable CY7C1363C-100AXC CY7C1361C-100AJXCChip Enable CY7C1363C-100AXI CY7C1361C-100AJXI CY7C1361C-100AXCPin Tqfp 14 x 20 x 1.4 mm Package DiagramsBall BGA 14 x 22 x 2.4 mm Soldernotespad Type NON-SOLDER Mask Defined Nsmd Document History Issue Date Orig. Description of Change