Cypress CY7C1363C Pin Configurations Pin Tqfp Pinout 3 Chip Enables a version, CY7C1361C 256K x

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CY7C1361C

CY7C1363C

Pin Configurations

100-Pin TQFP Pinout (3 Chip Enables) (A version)

DQPC

DQC

DQC

VDDQ

VSSQ

DQC

DQC

DQC

DQC

VSSQ

VDDQ

DQC DQC

VSS/DNU VDD NC VSS DQD DQD

VDDQ

VSSQ

DQD

DQD

DQD

DQD

VSSQ

VDDQ

DQD DQD DQPD

	A A CE						CE		BWD BWC BWB BWA CE V V CLK GW																BWE OE				ADSC	ADSP		ADV A A
1							2								3 DD SS
															3 DD SS



100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1																											80
2																											79
3																											78
4																											77
5																											76
6																											75
7																											74
8																											73
9																											72
10																											71
11																											70
12																											69
13																											68
14																											67
15													CY7C1361C														66
16													CY7C1361C														65
17														(256K x 36)													64
18																											63
19																											62
20																											61
21																											60
22																											59
23																											58
24																											57
25																											56
26																											55
27																											54
28																											53
29																											52
30																											51
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

DQPB	NC
DQB	NC
DQB	NC
VDDQ	VDDQ
VSSQ	VSSQ
DQB	NC
DQB	NC
DQB	DQB
DQB	DQB
VSSQ	VSSQ
VDDQ	VDDQ
DQB	DQB
DQB	DQ
VSS	B
VSS	VSS/DNU
NC	VDD
VDD	NC
ZZ	VSS
DQA	DQ
DQA	B
DQA	DQ
VDDQ	B
VDDQ	VDDQ
VSSQ	VSSQ
DQA	DQ
DQA	B
DQA	DQ
DQA	B
DQA	DQP
DQA	B
DQA	NC
VSSQ	VSSQ
VDDQ	VDDQ
DQA	NC
DQA	NC
DQPA	NC

1 2															3			DD SS								BWE				ADSC	ADSP
	A A								NC NC				BWB		BWA			DD SS																ADV A A
	A A				CE CE				NC NC				BWB		BWA	CE		V V CLK						GW				OE						ADV A A


100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1																														80
2																														79
3																														78
4																														77
5																														76
6																														75
7																														74
8																														73
9																														72
10																														71
11																														70
12																														69
13																														68
14															CY7C1363C															67
15															CY7C1363C															66
16															(512K x 18)															65
17															(512K x 18)															64
17																														64
18																														63
19																														62
20																														61
21																														60
22																														59
23																														58
24																														57
25																														56
26																														55
27																														54
28																														53
29																														52
30																														51
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

A

NC

NC

VDDQ VSSQ

NC DQPA DQA DQA

VSSQ VDDQ

DQA DQA

VSS

NC

VDD

ZZ

DQA

DQA

VDDQ

VSSQ

DQA

DQA

NC

NC

VSSQ VDDQ

NC

NC

NC

MODE A A A A A	A	NC NC V V NC A A A A A A A A
1	0	SS DD

1 0	SS DD	NC A A A A A A A A
MODE A A A A A A	NC NC V V	NC A A A A A A A A

Document #: 38-05541 Rev. *F

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Contents Cypress Semiconductor Corporation FeaturesSelection Guide Functional Description1 133 MHz 100 MHz UnitLogic Block Diagram CY7C1363C 512K x Logic Block Diagram CY7C1361C 256K xPin Configurations Pin Tqfp Pinout 3 Chip Enables a version CY7C1361C 256K xCY7C1363C 512K x CY7C1363C Pin Configurations Pin Tqfp Pinout 2 Chip Enables AJ VersionPin Configurations Ball BGA Pinout 2 Chip Enables with Jtag DQP B Pin Configurations Ball Fbga Pinout 3 Chip EnableBWE Adsc ADV CLKPower supply inputs to the core of the device Power supply for the I/O circuitryName Description Pin Definitions Ground for the core of the deviceGround for the I/O circuitry Address Interleaved Burst Address Table Mode = Floating or VDDFunctional Overview Burst SequencesZZ Mode Electrical Characteristics Parameter Description Test Conditions Min Max UnitAddress Cycle Description Used Function CY7C1363C Partial Truth Table for Read/Write3Truth Table for Read/Write3 Function CY7C1361CTAP Controller Block Diagram TAP Controller State DiagramIeee 1149.1 Serial Boundary Scan Jtag TAP Instruction Set Bypass RegisterSet-up Times TAP TimingParameter Min Max Unit Clock Output TimesIdentification Register Definitions TAP DC Electrical Characteristics And Operating Conditions3V TAP AC Test Conditions 5V TAP AC Test ConditionsInstruction Code Description Scan Register SizesIdentification Codes Register Name Bit Size xName CY7C1361C 256K x Bit # Ball ID SignalCY7C1363C 512K x Bit # Ball ID Signal Name Ball BGA Boundary Scan OrderBall Fbga Boundary Scan Order CY7C1361C 256K x Bit # Ball ID Signal NameAmbient Range Electrical Characteristics Over the Operating Range 13Maximum Ratings Operating Range3V I/O Test Load Capacitance15Thermal Resistance AC Test Loads and Waveforms133 100 Parameter Description Unit Min Max Switching Characteristics Over the Operating Range20GW, BWE,BWX Timing DiagramsRead Cycle Timing22 Adsc AddressDON’T Care Write Cycle Timing22Burst Read DON’T Care Undefined Read/Write Cycle Timing22, 24ZZ Mode Timing26 CY7C1361C-133AXC Chip Enable CY7C1363C-133AXC CY7C1361C-133AJXCChip Enable CY7C1363C-133AXI CY7C1361C-133AJXI Ordering InformationCY7C1361C-100AXE Chip Enable CY7C1363C-100AXC CY7C1361C-100AJXCChip Enable CY7C1363C-100AXI CY7C1361C-100AJXI CY7C1361C-100AXCPin Tqfp 14 x 20 x 1.4 mm Package DiagramsBall BGA 14 x 22 x 2.4 mm Soldernotespad Type NON-SOLDER Mask Defined Nsmd Document History Issue Date Orig. Description of Change