Cypress CY7C1363C, CY7C1361C manual Document History, Issue Date Orig. Description of Change

Page 31

CY7C1361C

CY7C1363C

Document History Page

Document Title: CY7C1361C/CY7C1363C 9-Mbit (256K x 36/512K x 18) Flow-Through SRAM

Document Number: 38-05541

REV.

ECN NO.

Issue Date

Orig. of

Description of Change

Change

 

 

 

 

 

**

241690

See ECN

RKF

New data sheet

 

 

 

 

 

*A

278969

See ECN

RKF

Changed Boundary Scan order to match the B rev of these devices.

 

 

 

 

 

*B

332059

See ECN

PCI

Removed 117-MHz Speed Bin

 

 

 

 

Address expansion pins/balls in the pinouts for all packages are modified

 

 

 

 

as per JEDEC standard

 

 

 

 

Added Address Expansion pins in the Pin Definitions Table

 

 

 

 

Changed Device Width (23:18) for 119-BGA from 000001 to 101001

 

 

 

 

Added separate row for 165 -FBGA Device Width (23:18)

 

 

 

 

Changed IDDZZ from 35 mA to 50 mA

 

 

 

 

Changed ISB1 and ISB3 from 40 mA to 110 and 100 mA, respectively

 

 

 

 

Modified VOL, VOH test conditions

 

 

 

 

Corrected ISB4 Test Condition from (VIN ≥ VDD – 0.3V or VIN ≤ 0.3V) to

 

 

 

 

(VIN ≥ VIH or VIN ≤ VIL) in the Electrical Characteristics table

 

 

 

 

Changed ΘJA and ΘJc for TQFP Package from 25 and 9 °C/W to 29.41

 

 

 

 

and 6.13 °C/W

 

 

 

 

respectively

 

 

 

 

Changed ΘJA and ΘJc for BGA Package from 25 and 6°C/W to 34.1 and

 

 

 

 

14.0 °C/W

 

 

 

 

respectively

 

 

 

 

Changed ΘJA and ΘJc for FBGA Package from 27 and 6 °C/W to 16.8

 

 

 

 

and 3.0 °C/W respectively

 

 

 

 

Added lead-free information for 100-pin TQFP, 119 BGA and 165 FBGA

 

 

 

 

packages

 

 

 

 

Updated Ordering Information Table

*C

377095

See ECN

PCI

Changed ISB2 from 30 to 40 mA

 

 

 

 

Modified test condition in note# 14 from VIH < VDD to VIH < VDD

*D

408298

See ECN

RXU

Changed address of Cypress Semiconductor Corporation on Page# 1

 

 

 

 

from “3901 North First Street” to “198 Champion Court”

 

 

 

 

Changed tri state to tri-state.

 

 

 

 

Modified “Input Load” to “Input Leakage Current except ZZ and MODE”

 

 

 

 

in the Electrical Characteristics Table.

 

 

 

 

Replaced Package Name column with Package Diagram in the Ordering

 

 

 

 

Information table.

 

 

 

 

Updated the ordering information.

*E

433033

See ECN

NXR

Included Automotive range.

 

 

 

 

 

*F

501793

See ECN

VKN

Added the Maximum Rating for Supply Voltage on VDDQ Relative to GND

 

 

 

 

Changed tTH, tTL from 25 ns to 20 ns and tTDOV from 5 ns to 10 ns in TAP

 

 

 

 

AC Switching Characteristics table.

 

 

 

 

Updated the Ordering Information table.

Document #: 38-05541 Rev. *F

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Contents Cypress Semiconductor Corporation FeaturesSelection Guide Functional Description1 133 MHz 100 MHz UnitLogic Block Diagram CY7C1363C 512K x Logic Block Diagram CY7C1361C 256K xCY7C1361C 256K x Pin Configurations Pin Tqfp Pinout 3 Chip Enables a versionCY7C1363C 512K x CY7C1363C Pin Configurations Pin Tqfp Pinout 2 Chip Enables AJ VersionPin Configurations Ball BGA Pinout 2 Chip Enables with Jtag DQP B Pin Configurations Ball Fbga Pinout 3 Chip EnableBWE Adsc ADV CLKPower supply for the I/O circuitry Power supply inputs to the core of the deviceName Description Ground for the core of the device Pin DefinitionsGround for the I/O circuitry Address Interleaved Burst Address Table Mode = Floating or VDDFunctional Overview Burst SequencesParameter Description Test Conditions Min Max Unit ZZ Mode Electrical CharacteristicsAddress Cycle Description Used Function CY7C1363C Partial Truth Table for Read/Write3Truth Table for Read/Write3 Function CY7C1361CTAP Controller State Diagram TAP Controller Block DiagramIeee 1149.1 Serial Boundary Scan Jtag TAP Instruction Set Bypass RegisterSet-up Times TAP TimingParameter Min Max Unit Clock Output TimesIdentification Register Definitions TAP DC Electrical Characteristics And Operating Conditions3V TAP AC Test Conditions 5V TAP AC Test ConditionsInstruction Code Description Scan Register SizesIdentification Codes Register Name Bit Size xName CY7C1361C 256K x Bit # Ball ID SignalCY7C1363C 512K x Bit # Ball ID Signal Name Ball BGA Boundary Scan OrderBall Fbga Boundary Scan Order CY7C1361C 256K x Bit # Ball ID Signal NameAmbient Range Electrical Characteristics Over the Operating Range 13Maximum Ratings Operating Range3V I/O Test Load Capacitance15Thermal Resistance AC Test Loads and Waveforms133 100 Parameter Description Unit Min Max Switching Characteristics Over the Operating Range20GW, BWE,BWX Timing DiagramsRead Cycle Timing22 Adsc AddressDON’T Care Write Cycle Timing22Burst Read DON’T Care Undefined Read/Write Cycle Timing22, 24ZZ Mode Timing26 CY7C1361C-133AXC Chip Enable CY7C1363C-133AXC CY7C1361C-133AJXCChip Enable CY7C1363C-133AXI CY7C1361C-133AJXI Ordering InformationCY7C1361C-100AXE Chip Enable CY7C1363C-100AXC CY7C1361C-100AJXCChip Enable CY7C1363C-100AXI CY7C1361C-100AJXI CY7C1361C-100AXCPin Tqfp 14 x 20 x 1.4 mm Package DiagramsBall BGA 14 x 22 x 2.4 mm Soldernotespad Type NON-SOLDER Mask Defined Nsmd Document History Issue Date Orig. Description of Change
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