Cypress CY7C1361C, CY7C1363C manual Read/Write Cycle Timing22, 24, Burst Read DON’T Care Undefined

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CY7C1361C

CY7C1363C

Timing Diagrams (continued)

Read/Write Cycle Timing[22, 24, 25]

tCYC

CLK

tt

CH CL

tADS tADH

ADSP

ADSC

tAS tAH

ADDRESS	A1	A2	A3		A4
				tWES	tWEH
BWE, BWX
		tCES tCEH
CE
ADV
OE
				tDS	tDH
					tOELZ
Data In (D)		High-Z	t	D(A3)
			OEHZ		tCDV
					tCDV
Data Out (Q)		Q(A1)	Q(A2)		Q(A4)	Q(A4+1)	Q(A4+2)	Q(A4+3)
		Back-to-Back READs		Single WRITE		BURST READ
					DON’T CARE	UNDEFINED

Notes:

24.The data bus (Q) remains in high-Z following a WRITE cycle, unless a new read access is initiated by ADSP or ADSC.

25.GW is HIGH.

A5 A6

D(A5) D(A6)

Back-to-Back

WRITEs

Document #: 38-05541 Rev. *F

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Contents Features Selection Guide Functional Description1133 MHz 100 MHz Unit Cypress Semiconductor CorporationLogic Block Diagram CY7C1361C 256K x Logic Block Diagram CY7C1363C 512K xPin Configurations Pin Tqfp Pinout 3 Chip Enables a version CY7C1361C 256K xCY7C1363C 512K x Pin Configurations Pin Tqfp Pinout 2 Chip Enables AJ Version CY7C1363CPin Configurations Ball BGA Pinout 2 Chip Enables with Jtag Pin Configurations Ball Fbga Pinout 3 Chip Enable BWE Adsc ADVCLK DQP BPower supply inputs to the core of the device Power supply for the I/O circuitryName Description Pin Definitions Ground for the core of the deviceGround for the I/O circuitry Interleaved Burst Address Table Mode = Floating or VDD Functional OverviewBurst Sequences AddressZZ Mode Electrical Characteristics Parameter Description Test Conditions Min Max UnitAddress Cycle Description Used Partial Truth Table for Read/Write3 Truth Table for Read/Write3Function CY7C1361C Function CY7C1363CTAP Controller Block Diagram TAP Controller State DiagramIeee 1149.1 Serial Boundary Scan Jtag Bypass Register TAP Instruction SetTAP Timing Parameter Min Max Unit ClockOutput Times Set-up TimesTAP DC Electrical Characteristics And Operating Conditions 3V TAP AC Test Conditions5V TAP AC Test Conditions Identification Register DefinitionsScan Register Sizes Identification CodesRegister Name Bit Size x Instruction Code DescriptionCY7C1361C 256K x Bit # Ball ID Signal CY7C1363C 512K x Bit # Ball ID Signal NameBall BGA Boundary Scan Order NameCY7C1361C 256K x Bit # Ball ID Signal Name Ball Fbga Boundary Scan OrderElectrical Characteristics Over the Operating Range 13 Maximum RatingsOperating Range Ambient RangeCapacitance15 Thermal ResistanceAC Test Loads and Waveforms 3V I/O Test LoadSwitching Characteristics Over the Operating Range20 133 100 Parameter Description Unit Min MaxTiming Diagrams Read Cycle Timing22Adsc Address GW, BWE,BWXWrite Cycle Timing22 DON’T CareRead/Write Cycle Timing22, 24 Burst Read DON’T Care UndefinedZZ Mode Timing26 Chip Enable CY7C1363C-133AXC CY7C1361C-133AJXC Chip Enable CY7C1363C-133AXI CY7C1361C-133AJXIOrdering Information CY7C1361C-133AXCChip Enable CY7C1363C-100AXC CY7C1361C-100AJXC Chip Enable CY7C1363C-100AXI CY7C1361C-100AJXICY7C1361C-100AXC CY7C1361C-100AXEPackage Diagrams Pin Tqfp 14 x 20 x 1.4 mmBall BGA 14 x 22 x 2.4 mm Soldernotespad Type NON-SOLDER Mask Defined Nsmd Issue Date Orig. Description of Change Document History