Cypress CY7C1363C, CY7C1361C manual Pin Configurations Ball BGA Pinout 2 Chip Enables with Jtag

Page 5

CY7C1361C

CY7C1363C

Pin Configurations (continued)

119-Ball BGA Pinout (2 Chip Enables with JTAG)

CY7C1361C (256K x 36)

 

1

2

3

 

4

 

 

 

 

 

 

 

5

 

 

6

7

A

VDDQ

A

 

A

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A

A

VDDQ

 

ADSP

B

NC/288M

CE2

 

A

 

 

 

 

 

 

 

 

 

 

 

 

 

A

A

NC/512M

 

ADSC

C

NC/144M

A

 

A

 

 

 

 

VDD

 

A

A

NC/1G

D

DQC

DQPC

 

VSS

 

 

 

 

 

NC

 

VSS

DQPB

DQB

E

DQC

DQC

 

VSS

 

 

 

 

 

 

1

 

 

 

VSS

DQB

DQB

 

 

 

 

CE

F

VDDQ

DQC

 

VSS

 

 

 

 

 

 

 

 

 

 

 

VSS

DQB

VDDQ

 

 

 

 

 

OE

G

DQC

DQC

 

 

C

 

 

 

 

 

 

 

 

 

 

 

B

DQB

DQB

BW

 

 

 

ADV

BW

H

DQC

DQC

 

VSS

 

 

 

 

 

 

 

 

VSS

DQB

DQB

 

 

 

 

GW

J

VDDQ

VDD

 

NC

 

 

 

 

VDD

 

NC

VDD

VDDQ

K

DQD

DQD

 

VSS

 

 

 

CLK

 

VSS

DQA

DQA

L

DQD

DQD

 

 

D

 

 

 

 

 

NC

 

 

A

DQA

DQA

 

BW

 

 

 

 

 

 

BW

M

VDDQ

DQD

 

VSS

 

 

 

 

 

VSS

DQA

VDDQ

 

 

 

BWE

 

N

DQD

DQD

 

VSS

 

 

 

 

 

A1

 

VSS

DQA

DQA

P

DQD

DQPD

 

VSS

 

 

 

 

 

A0

 

VSS

DQPA

DQA

R

NC

A

MODE

 

 

 

 

VDD

 

NC

A

NC

T

NC

NC/72M

 

A

 

 

 

 

 

A

 

A

NC/36M

ZZ

U

VDDQ

TMS

 

TDI

 

 

 

TCK

 

TDO

NC

VDDQ

CY7C1363C (512K x 18)

 

1

2

3

 

4

 

 

 

 

 

 

 

5

 

6

7

A

VDDQ

A

 

A

 

 

 

 

 

 

 

 

 

 

 

 

 

A

A

VDDQ

 

ADSP

B

NC/288M

CE2

 

A

 

 

 

 

 

 

 

 

 

 

 

 

A

A

NC/512M

 

ADSC

C

NC/144M

A

 

A

 

 

 

VDD

 

A

A

NC/1G

D

DQB

NC

 

VSS

 

 

 

 

NC

 

VSS

DQPA

NC

E

NC

DQB

 

VSS

 

 

 

 

 

1

 

 

 

VSS

NC

DQA

 

 

 

CE

F

VDDQ

NC

 

VSS

 

 

 

 

 

 

 

 

 

 

VSS

DQA

VDDQ

 

 

 

 

OE

G

NC

DQB

 

 

B

 

 

 

 

 

 

 

 

VSS

NC

DQA

BW

 

 

ADV

H

DQB

NC

 

VSS

 

 

 

 

 

 

 

VSS

DQA

NC

 

 

 

GW

J

VDDQ

VDD

 

NC

 

 

 

VDD

 

NC

VDD

VDDQ

K

NC

DQB

 

VSS

 

 

CLK

 

VSS

NC

DQA

L

DQB

NC

 

VSS

 

 

 

 

NC

 

 

A

DQA

NC

 

 

 

 

 

 

BW

M

VDDQ

DQB

 

VSS

 

 

 

 

 

VSS

NC

VDDQ

 

 

 

BWE

 

N

DQB

NC

 

VSS

 

 

 

 

A1

 

VSS

DQA

NC

P

NC

DQPB

 

VSS

 

 

 

 

A0

 

VSS

NC

DQA

R

NC

A

MODE

 

 

 

VDD

 

NC

A

NC

T

NC/72M

A

 

A

NC/36M

 

A

A

ZZ

U

VDDQ

TMS

 

TDI

 

 

TCK

 

TDO

NC

VDDQ

Document #: 38-05541 Rev. *F

Page 5 of 31

[+] Feedback

Image 5
Contents Selection Guide Functional Description1 Features133 MHz 100 MHz Unit Cypress Semiconductor CorporationLogic Block Diagram CY7C1363C 512K x Logic Block Diagram CY7C1361C 256K xCY7C1363C 512K x Pin Configurations Pin Tqfp Pinout 3 Chip Enables a versionCY7C1361C 256K x CY7C1363C Pin Configurations Pin Tqfp Pinout 2 Chip Enables AJ VersionPin Configurations Ball BGA Pinout 2 Chip Enables with Jtag BWE Adsc ADV Pin Configurations Ball Fbga Pinout 3 Chip EnableCLK DQP BName Description Power supply inputs to the core of the devicePower supply for the I/O circuitry Ground for the I/O circuitry Pin DefinitionsGround for the core of the device Functional Overview Interleaved Burst Address Table Mode = Floating or VDDBurst Sequences AddressAddress Cycle Description Used ZZ Mode Electrical CharacteristicsParameter Description Test Conditions Min Max Unit Truth Table for Read/Write3 Partial Truth Table for Read/Write3Function CY7C1361C Function CY7C1363CIeee 1149.1 Serial Boundary Scan Jtag TAP Controller Block DiagramTAP Controller State Diagram TAP Instruction Set Bypass RegisterParameter Min Max Unit Clock TAP TimingOutput Times Set-up Times3V TAP AC Test Conditions TAP DC Electrical Characteristics And Operating Conditions5V TAP AC Test Conditions Identification Register DefinitionsIdentification Codes Scan Register SizesRegister Name Bit Size x Instruction Code DescriptionCY7C1363C 512K x Bit # Ball ID Signal Name CY7C1361C 256K x Bit # Ball ID SignalBall BGA Boundary Scan Order NameBall Fbga Boundary Scan Order CY7C1361C 256K x Bit # Ball ID Signal NameMaximum Ratings Electrical Characteristics Over the Operating Range 13Operating Range Ambient RangeThermal Resistance Capacitance15AC Test Loads and Waveforms 3V I/O Test Load133 100 Parameter Description Unit Min Max Switching Characteristics Over the Operating Range20Read Cycle Timing22 Timing DiagramsAdsc Address GW, BWE,BWXDON’T Care Write Cycle Timing22Burst Read DON’T Care Undefined Read/Write Cycle Timing22, 24ZZ Mode Timing26 Chip Enable CY7C1363C-133AXI CY7C1361C-133AJXI Chip Enable CY7C1363C-133AXC CY7C1361C-133AJXCOrdering Information CY7C1361C-133AXCChip Enable CY7C1363C-100AXI CY7C1361C-100AJXI Chip Enable CY7C1363C-100AXC CY7C1361C-100AJXCCY7C1361C-100AXC CY7C1361C-100AXEPin Tqfp 14 x 20 x 1.4 mm Package DiagramsBall BGA 14 x 22 x 2.4 mm Soldernotespad Type NON-SOLDER Mask Defined Nsmd Document History Issue Date Orig. Description of Change