Cypress CY7C1361C, CY7C1363C manual Package Diagrams, Pin Tqfp 14 x 20 x 1.4 mm

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CY7C1361C

CY7C1363C

Package Diagrams

100-Pin TQFP (14 x 20 x 1.4 mm) (51-85050)

16.00±0.20

14.00±0.10

1.40±0.05

100	81
1	80

22.00±0.20

20.00±0.10

30

31

0.30±0.08

0.65	12° ±1°
TYP.	(8X)

51

50

SEE DETAIL

A

0.20 MAX.

1.60 MAX.

R 0.08 MIN. 0.20 MAX.

0.25

0° MIN.

SEATING PLANE

STAND-OFF

0.05 MIN.NOTE:

0.15 MAX.

0.10

GAUGE PLANE

0° -7°

0.60±0.15

1.00 REF.

R 0.08 MIN. 0.20 MAX.

0.20 MIN.

DETAIL A

1.JEDEC STD REF MS-026

2.BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH

3.DIMENSIONS IN MILLIMETERS

51-85050-*B

Document #: 38-05541 Rev. *F

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Contents Features Selection Guide Functional Description1133 MHz 100 MHz Unit Cypress Semiconductor CorporationLogic Block Diagram CY7C1361C 256K x Logic Block Diagram CY7C1363C 512K xCY7C1361C 256K x Pin Configurations Pin Tqfp Pinout 3 Chip Enables a versionCY7C1363C 512K x Pin Configurations Pin Tqfp Pinout 2 Chip Enables AJ Version CY7C1363CPin Configurations Ball BGA Pinout 2 Chip Enables with Jtag Pin Configurations Ball Fbga Pinout 3 Chip Enable BWE Adsc ADVCLK DQP BPower supply for the I/O circuitry Power supply inputs to the core of the deviceName Description Ground for the core of the device Pin DefinitionsGround for the I/O circuitry Interleaved Burst Address Table Mode = Floating or VDD Functional OverviewBurst Sequences AddressParameter Description Test Conditions Min Max Unit ZZ Mode Electrical CharacteristicsAddress Cycle Description Used Partial Truth Table for Read/Write3 Truth Table for Read/Write3Function CY7C1361C Function CY7C1363CTAP Controller State Diagram TAP Controller Block DiagramIeee 1149.1 Serial Boundary Scan Jtag Bypass Register TAP Instruction SetTAP Timing Parameter Min Max Unit ClockOutput Times Set-up TimesTAP DC Electrical Characteristics And Operating Conditions 3V TAP AC Test Conditions5V TAP AC Test Conditions Identification Register DefinitionsScan Register Sizes Identification CodesRegister Name Bit Size x Instruction Code DescriptionCY7C1361C 256K x Bit # Ball ID Signal CY7C1363C 512K x Bit # Ball ID Signal NameBall BGA Boundary Scan Order NameCY7C1361C 256K x Bit # Ball ID Signal Name Ball Fbga Boundary Scan OrderElectrical Characteristics Over the Operating Range 13 Maximum RatingsOperating Range Ambient RangeCapacitance15 Thermal ResistanceAC Test Loads and Waveforms 3V I/O Test LoadSwitching Characteristics Over the Operating Range20 133 100 Parameter Description Unit Min MaxTiming Diagrams Read Cycle Timing22Adsc Address GW, BWE,BWXWrite Cycle Timing22 DON’T CareRead/Write Cycle Timing22, 24 Burst Read DON’T Care UndefinedZZ Mode Timing26 Chip Enable CY7C1363C-133AXC CY7C1361C-133AJXC Chip Enable CY7C1363C-133AXI CY7C1361C-133AJXIOrdering Information CY7C1361C-133AXCChip Enable CY7C1363C-100AXC CY7C1361C-100AJXC Chip Enable CY7C1363C-100AXI CY7C1361C-100AJXICY7C1361C-100AXC CY7C1361C-100AXEPackage Diagrams Pin Tqfp 14 x 20 x 1.4 mmBall BGA 14 x 22 x 2.4 mm Soldernotespad Type NON-SOLDER Mask Defined Nsmd Issue Date Orig. Description of Change Document History