Cypress CY7C0850AV, CY7C0852AV Switching Characteristics, Normal Load Load Three-state Delay Load

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CY7C0850AV, CY7C0851AV

CY7C0852AV, CY7C0853AV

Figure 6. AC Test Load and Waveforms

Z0 = 50Ω

OUTPUT

C = 10 pF

3.3V

R = 50Ω

R1 = 590 Ω

OUTPUT

VTH = 1.5V

C = 5 pF

R2 = 435

Ω

(a) Normal Load (Load 1)

(b) Three-state Delay (Load 2)

ALL INPUT PULSES

3.0V

VSS

< 2 ns


		90%			90%

							10%
	10%

< 2 ns

Switching Characteristics

Over the Operating Range

-167

-133

-100

Parameter

Description

CY7C0850AV

CY7C0850AV

CY7C0853AV

CY7C0853AV

Unit

CY7C0851AV

CY7C0851AV

CY7C0852AV

CY7C0852AV

Min

Max

Min

Max

Min

Max

Min

Max

fMAX2

Maximum Operating Frequency

167

133

133

100

MHz

tCYC2

Clock Cycle Time

6.0

7.5

7.5

10.0

ns

tCH2

Clock HIGH Time

2.7

3.0

3.0

4.0

ns

tCL2

Clock LOW Time

2.7

3.0

3.0

4.0

ns

tR[19]

Clock Rise Time

2.0

2.0

2.0

3.0

ns

tF[19]

Clock Fall Time

2.0

2.0

2.0

3.0

ns

tSA

Address Setup Time

2.3

2.5

2.5

3.0

ns

tHA

Address Hold Time

0.6

0.6

0.6

0.6

ns

tSB

Byte Select Setup Time

2.3

2.5

2.5

3.0

ns

tHB

Byte Select Hold Time

0.6

0.6

0.6

0.6

ns

tSC

Chip Enable Setup Time

2.3

2.5

NA

NA

ns

tHC

Chip Enable Hold Time

0.6

0.6

NA

NA

ns

tSW

R/W

Setup Time

2.3

2.5

2.5

3.0

ns

tHW

R/W

Hold Time

0.6

0.6

0.6

0.6

ns

tSD

Input Data Setup Time

2.3

2.5

2.5

3.0

ns

tHD

Input Data Hold Time

0.6

0.6

0.6

0.6

ns

tSAD

ADS

Setup Time

2.3

2.5

NA

NA

ns

tHAD

ADS

Hold Time

0.6

0.6

NA

NA

ns

tSCN

CNTEN

Setup Time

2.3

2.5

NA

NA

ns

tHCN

CNTEN

Hold Time

0.6

0.6

NA

NA

ns

tSRST

CNTRST

Setup Time

2.3

2.5

NA

NA

ns

tHRST

CNTRST

Hold Time

0.6

0.6

NA

NA

ns

tSCM

CNT/MSK

Setup Time

2.3

2.5

NA

NA

ns

tHCM

CNT/MSK

Hold Time

0.6

0.6

NA

NA

ns

Note

19. Except JTAG signals (tr and tf < 10 ns [max.]).

Document #: 38-06070 Rev. *H

Page 14 of 32

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Contents 176TQFP 172FBGA Functional DescriptionProduct Selection Guide Density Mbit 32K x 64K x 128K x Cypress Semiconductor Corporation 198 Champion CourtRAM Array Logic Block DiagramTrue Mirror RegPin Configurations Ball BGA Top ViewCY7C0853AV CY7C0850AV CY7C0851AV CY7C0852AV Pin Definitions Operation Description Master ResetMailbox Interrupts Address Counter and Mask Register Operations Retransmit Mask Reset OperationCounter Interrupt Mask Load OperationCnten ADS Cntrst Mrst CLKProgrammable Counter-Mask Register Operation 1 Performing a TAP Reset Ieee 1149.1 Serial Boundary Scan JtagOperating Range Electrical CharacteristicsMaximum Ratings CapacitanceSwitching Characteristics Normal Load Load Three-state Delay LoadPort to Port Delays Master Reset TimingJtag Timing Parameter Description 167/133/100 Unit MinSwitching Waveforms Master ResetBank Select Read 26 Read-to-Write-to-Read OE Controlled 25, 28, 30 Write with Address Counter Advance Disabled-to-Write-to-Read-to-Write-to-Read Read-to-Readback-to-Read-to-Read R/W = High Counter Reset 32 Readback State of Address Counter or Mask Register35, 36, 37 LeftPort LPort Write to RightPort RPort Read39, 40 Counter Interrupt and Retransmit 34, 42, 43, 44 CLK 128K × 36 4M 3.3V Synchronous CY7C0852AV Dual-Port Sram Ordering Information256K × 36 9M 3.3V Synchronous CY7C0853AV Dual-Port Sram 64K × 36 2M 3.3V Synchronous CY7C0851AV Dual-Port SramPackage Diagrams Ball Fbga 15 x 15 x 1.25 mmPin Thin Quad Flat Pack 24 × 24 × 1.4 mm Document History Submis Orig. Description of Change Sion DateUSB Sales, Solutions, and Legal InformationWorldwide Sales and Design Support Products PSoC Solutions