Cypress CY7C0852AV, CY7C0853AV, CY7C0850AV, CY7C0851AV manual Write with Address Counter Advance

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CY7C0850AV, CY7C0851AV

CY7C0852AV, CY7C0853AV

Switching Waveforms (continued)

Figure 14. Write with Address Counter Advance [31]

tCYC2

CLK

tCH2

tCL2

tSA

tHA

ADDRESS

An

INTERNAL

An

An+1

An+2

An+3

An+4

ADDRESS

tSAD

tHAD

ADS

CNTEN

tSCN

tHCN

DATA	Dn	Dn+1	Dn+1	Dn+2	Dn+3	Dn+4
IN

tSD

tHD

WRITE EXTERNAL

WRITE WITH

WRITE COUNTER

WRITE WITH COUNTER

ADDRESS

COUNTER

HOLD

Figure 15. Disabled-to-Read-to-Read-to-Read-to-Write

tCYC2

tCL2 tCH2

CLK

tSC

tHC

CE

						tSW	tHW
R/W
	tSW	tHW
t		t			t	SA	tHA
SA		HA				SA
ADDRESS	An		An+1	An+2		An+3		An+4
OE
						tSD tHD
DATAIN						Dn+3
DATAOUT			tCD2		Qn+1
DATAOUT				Qn				Qn+2
				Qn				Qn+2
DISABLED		READ		READ	READ		WRITE	READ

Document #: 38-06070 Rev. *H

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Contents Functional Description Product Selection Guide Density Mbit 32K x 64K x 128K x176TQFP 172FBGA Cypress Semiconductor Corporation 198 Champion CourtLogic Block Diagram TrueRAM Array Mirror RegPin Configurations Ball BGA Top ViewCY7C0853AV CY7C0850AV CY7C0851AV CY7C0852AV Pin Definitions Operation Description Master ResetMailbox Interrupts Address Counter and Mask Register Operations Mask Reset Operation Counter InterruptRetransmit Mask Load OperationCnten ADS Cntrst Mrst CLKProgrammable Counter-Mask Register Operation 1 Performing a TAP Reset Ieee 1149.1 Serial Boundary Scan JtagElectrical Characteristics Maximum RatingsOperating Range CapacitanceSwitching Characteristics Normal Load Load Three-state Delay LoadPort to Port Delays Master Reset TimingJtag Timing Parameter Description 167/133/100 Unit MinSwitching Waveforms Master ResetBank Select Read 26 Read-to-Write-to-Read OE Controlled 25, 28, 30 Write with Address Counter Advance Disabled-to-Write-to-Read-to-Write-to-Read Read-to-Readback-to-Read-to-Read R/W = High Counter Reset 32 Readback State of Address Counter or Mask Register35, 36, 37 LeftPort LPort Write to RightPort RPort Read39, 40 Counter Interrupt and Retransmit 34, 42, 43, 44 CLK Ordering Information 256K × 36 9M 3.3V Synchronous CY7C0853AV Dual-Port Sram128K × 36 4M 3.3V Synchronous CY7C0852AV Dual-Port Sram 64K × 36 2M 3.3V Synchronous CY7C0851AV Dual-Port SramPackage Diagrams Ball Fbga 15 x 15 x 1.25 mmPin Thin Quad Flat Pack 24 × 24 × 1.4 mm Document History Submis Orig. Description of Change Sion DateUSB Sales, Solutions, and Legal InformationWorldwide Sales and Design Support Products PSoC Solutions