Cypress CY7C0853AV, CY7C0852AV, CY7C0850AV manual Package Diagrams, Ball Fbga 15 x 15 x 1.25 mm

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CY7C0850AV, CY7C0851AV

CY7C0852AV, CY7C0853AV

Package Diagrams

Figure 24. 172-Ball FBGA (15 x 15 x 1.25 mm) (51-85114)

51-85114-*B

Document #: 38-06070 Rev. *H

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Contents Product Selection Guide Density Mbit 32K x 64K x 128K x Functional Description176TQFP 172FBGA Cypress Semiconductor Corporation 198 Champion CourtTrue Logic Block DiagramRAM Array Mirror RegBall BGA Top View Pin ConfigurationsCY7C0853AV CY7C0850AV CY7C0851AV CY7C0852AV Pin Definitions Operation Description Master ResetMailbox Interrupts Address Counter and Mask Register Operations Counter Interrupt Mask Reset OperationRetransmit Mask Load OperationCLK Cnten ADS Cntrst MrstProgrammable Counter-Mask Register Operation 1 Ieee 1149.1 Serial Boundary Scan Jtag Performing a TAP ResetMaximum Ratings Electrical CharacteristicsOperating Range CapacitanceNormal Load Load Three-state Delay Load Switching CharacteristicsMaster Reset Timing Port to Port DelaysParameter Description 167/133/100 Unit Min Jtag TimingMaster Reset Switching WaveformsBank Select Read 26 Read-to-Write-to-Read OE Controlled 25, 28, 30 Write with Address Counter Advance Disabled-to-Write-to-Read-to-Write-to-Read Read-to-Readback-to-Read-to-Read R/W = High Counter Reset 32 Readback State of Address Counter or Mask Register35, 36, 37 LeftPort LPort Write to RightPort RPort Read39, 40 Counter Interrupt and Retransmit 34, 42, 43, 44 CLK 256K × 36 9M 3.3V Synchronous CY7C0853AV Dual-Port Sram Ordering Information128K × 36 4M 3.3V Synchronous CY7C0852AV Dual-Port Sram 64K × 36 2M 3.3V Synchronous CY7C0851AV Dual-Port SramBall Fbga 15 x 15 x 1.25 mm Package DiagramsPin Thin Quad Flat Pack 24 × 24 × 1.4 mm Submis Orig. Description of Change Sion Date Document HistoryUSB Sales, Solutions, and Legal InformationWorldwide Sales and Design Support Products PSoC Solutions