Cypress CY7C0851AV, CY7C0852AV, CY7C0853AV, CY7C0850AV manual Counter Reset 32

Page 23

 

 

 

 

 

 

 

CY7C0850AV, CY7C0851AV

 

 

 

 

 

 

 

CY7C0852AV, CY7C0853AV

Switching Waveforms (continued)

 

 

 

 

 

 

 

 

 

 

 

Figure 19. Counter Reset[32, 33]

 

 

 

 

 

 

 

 

tCYC2

 

 

 

 

 

 

 

 

 

 

tCH2

tCL2

 

 

 

 

 

 

 

CLK

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tSA

tHA

 

 

ADDRESS

 

 

 

 

 

 

An

 

Am

 

Ap

INTERNAL

A

x

 

 

0

1

A

n

A

m

Ap

ADDRESS

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tSW

tHW

 

 

 

 

 

 

R/W

 

 

 

 

 

 

 

 

 

 

 

ADS

 

 

 

 

 

 

 

 

 

 

 

CNTEN

 

 

 

 

 

 

 

 

 

 

 

 

tSRST

tHRST

 

 

 

 

 

 

 

 

CNTRST

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tSD

tHD

 

 

 

 

 

 

DATAIN

 

 

 

D0

tCD2

tCD2

 

 

 

 

DATAOUT[34]

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Q

 

0

 

Q

Q

 

n

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

COUNTER

WRITE

tCKLZ

 

 

 

READ

 

 

 

 

READ

 

READ

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

READ

 

 

 

 

 

 

 

 

 

 

 

 

RESET

ADDRESS 0

ADDRESS 0

 

ADDRESS 1

 

 

 

ADDRESS An

ADDRESS Am

 

 

 

Notes

32.CE0 = B0 – B3 = LOW; CE1 = MRST = CNT/MSK = HIGH.

33.No dead cycle exists during counter reset. A Read or Write cycle may be coincidental with the counter reset.

34.Retransmit happens if the counter remains in increment mode after it wraps to initially loaded value.

Document #: 38-06070 Rev. *H

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Contents Cypress Semiconductor Corporation 198 Champion Court Functional DescriptionProduct Selection Guide Density Mbit 32K x 64K x 128K x 176TQFP 172FBGAMirror Reg Logic Block DiagramTrue RAM ArrayBall BGA Top View Pin ConfigurationsCY7C0853AV CY7C0850AV CY7C0851AV CY7C0852AV Pin Definitions Operation Description Master ResetMailbox Interrupts Address Counter and Mask Register Operations Mask Load Operation Mask Reset OperationCounter Interrupt RetransmitCLK Cnten ADS Cntrst MrstProgrammable Counter-Mask Register Operation 1 Ieee 1149.1 Serial Boundary Scan Jtag Performing a TAP ResetCapacitance Electrical CharacteristicsMaximum Ratings Operating RangeNormal Load Load Three-state Delay Load Switching CharacteristicsMaster Reset Timing Port to Port DelaysParameter Description 167/133/100 Unit Min Jtag TimingMaster Reset Switching WaveformsBank Select Read 26 Read-to-Write-to-Read OE Controlled 25, 28, 30 Write with Address Counter Advance Disabled-to-Write-to-Read-to-Write-to-Read Read-to-Readback-to-Read-to-Read R/W = High Counter Reset 32 Readback State of Address Counter or Mask Register35, 36, 37 LeftPort LPort Write to RightPort RPort Read39, 40 Counter Interrupt and Retransmit 34, 42, 43, 44 CLK 64K × 36 2M 3.3V Synchronous CY7C0851AV Dual-Port Sram Ordering Information256K × 36 9M 3.3V Synchronous CY7C0853AV Dual-Port Sram 128K × 36 4M 3.3V Synchronous CY7C0852AV Dual-Port SramBall Fbga 15 x 15 x 1.25 mm Package DiagramsPin Thin Quad Flat Pack 24 × 24 × 1.4 mm Submis Orig. Description of Change Sion Date Document HistoryUSB Sales, Solutions, and Legal InformationWorldwide Sales and Design Support Products PSoC Solutions
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