Cypress CY7C0850AV, CY7C0852AV, CY7C0853AV, CY7C0851AV manual Pin Definitions

Page 6

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CY7C0850AV, CY7C0851AV

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CY7C0852AV, CY7C0853AV

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Pin Definitions

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Left Port

 

 

 

Right Port

 

 

 

 

Description

 

A0L–A17L[1]

 

A0R–A17R[1]

 

 

Address Inputs.

 

ADSL[3]

 

ADSR[3]

 

 

 

 

Address Strobe Input. Used as an address qualifier. This signal should be asserted LOW for

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

the part using the externally supplied address on the address pins and for loading this address

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

into the burst address counter.

 

 

 

 

 

 

 

L[3]

 

 

 

 

 

 

 

R[3]

 

 

 

 

Active LOW Chip Enable Input.

 

CE0

CE0

 

 

 

 

CE1L[3]

 

CE1R[3]

 

 

 

 

Active HIGH Chip Enable Input.

 

CLKL

 

CLKR

 

 

 

 

Clock Signal. Maximum clock input rate is fMAX.

 

CNTEN [3]

 

CNTEN

[3]

 

 

Counter Enable Input. Asserting this signal LOW increments the burst address counter of its

 

 

 

 

 

 

 

 

 

 

 

L

 

 

 

 

 

 

 

 

 

R

 

 

 

 

respective port on each rising edge of CLK. The increment is disabled if ADS or CNTRST are

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

asserted LOW.

 

 

 

 

 

 

 

 

CNTRSTL[3]

 

CNTRSTR[3]

 

 

Counter Reset Input. Asserting this signal LOW resets to zero the unmasked portion of the burst

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

address counter of its respective port. CNTRST is not disabled by asserting ADS or CNTEN.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Address Counter Mask Register Enable Input. Asserting this signal LOW enables access to

 

CNT/MSK

[3]

 

CNT/MSK [3]

 

 

 

 

 

 

 

 

 

 

 

 

 

 

L

 

 

 

 

 

 

 

 

 

 

 

 

R

 

 

the mask register. When tied HIGH, the mask register is not accessible and the address counter

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

operations are enabled based on the status of the counter control signals.

 

 

 

 

 

 

 

 

DQ0L–DQ35L

 

DQ0R–DQ35R

 

 

Data Bus Input/Output.

 

 

 

 

L

 

 

 

 

R

 

 

 

 

Output Enable Input. This asynchronous signal must be asserted LOW to enable the DQ data

 

OE

OE

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

pins during Read operations.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Mailbox Interrupt Flag Output. The mailbox permits communications between ports. The upper

 

INTL

 

INTR

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

two memory locations can be used for message passing. INTL is asserted LOW when the right

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

port writes to the mailbox location of the left port, and vice versa. An interrupt to a port is

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

deasserted HIGH when it reads the contents of its mailbox.

 

CNTINT [3]

 

 

 

 

 

 

 

 

 

 

 

[3]

 

 

Counter Interrupt Output. This pin is asserted LOW when the unmasked portion of the counter

 

CNTINT

 

 

 

 

 

 

 

 

 

 

 

 

L

 

 

 

 

 

 

 

 

 

 

R

 

 

is incremented to all “1s.”

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

L

 

 

 

 

 

 

R

 

 

 

 

Read/Write Enable Input. Assert this pin LOW to write to, or HIGH to Read from the dual port

 

R/W

R/W

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

memory array.

 

 

 

 

 

 

 

 

 

 

3L

 

 

 

 

 

 

 

 

 

3R

 

 

 

 

Byte Select Inputs. Asserting these signals enables Read and Write operations to the corre-

 

B

0L–B

B

0R–B

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

sponding bytes of the memory array.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Master Reset Input.

 

is an asynchronous input signal and affects both ports. Asserting

 

MRST

 

 

 

 

 

 

 

 

 

 

 

 

 

MRST

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

MRST LOW performs all of the reset functions as described in the text. A MRST operation is

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

required at power up.

 

TMS

 

 

 

 

 

 

 

 

 

 

 

 

 

 

JTAG Test Mode Select Input. It controls the advance of JTAG TAP state machine. State

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

machine transitions occur on the rising edge of TCK.

 

TDI

 

 

 

 

 

 

 

 

 

 

 

 

 

 

JTAG Test Data Input. Data on the TDI input is shifted serially into selected registers.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TCK

 

 

 

 

 

 

 

 

 

 

 

 

 

 

JTAG Test Clock Input.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TDO

 

 

 

 

 

 

 

 

 

 

 

 

 

 

JTAG Test Data Output. TDO transitions occur on the falling edge of TCK. TDO is normally

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

three-stated except when captured data is shifted out of the JTAG TAP.

 

VSS

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Ground Inputs.

 

VDD

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Power Inputs.

Note

3. These pins are not available for CY7C0853AV device.

Document #: 38-06070 Rev. *H

Page 6 of 32

[+] Feedback

Page 5 Page 7
Image 6
Page 5 Page 7
Contents 176TQFP 172FBGA Functional DescriptionProduct Selection Guide Density Mbit 32K x 64K x 128K x Cypress Semiconductor Corporation 198 Champion CourtRAM Array Logic Block DiagramTrue Mirror RegPin Configurations Ball BGA Top ViewCY7C0853AV CY7C0850AV CY7C0851AV CY7C0852AV Pin Definitions Master Reset Mailbox InterruptsOperation Description Address Counter and Mask Register Operations Retransmit Mask Reset OperationCounter Interrupt Mask Load OperationCnten ADS Cntrst Mrst CLKProgrammable Counter-Mask Register Operation 1 Performing a TAP Reset Ieee 1149.1 Serial Boundary Scan JtagOperating Range Electrical CharacteristicsMaximum Ratings CapacitanceSwitching Characteristics Normal Load Load Three-state Delay LoadPort to Port Delays Master Reset TimingJtag Timing Parameter Description 167/133/100 Unit MinSwitching Waveforms Master ResetBank Select Read 26 Read-to-Write-to-Read OE Controlled 25, 28, 30 Write with Address Counter Advance Disabled-to-Write-to-Read-to-Write-to-Read Read-to-Readback-to-Read-to-Read R/W = High Counter Reset 32 Readback State of Address Counter or Mask Register35, 36, 37 LeftPort LPort Write to RightPort RPort Read39, 40 Counter Interrupt and Retransmit 34, 42, 43, 44 CLK 128K × 36 4M 3.3V Synchronous CY7C0852AV Dual-Port Sram Ordering Information256K × 36 9M 3.3V Synchronous CY7C0853AV Dual-Port Sram 64K × 36 2M 3.3V Synchronous CY7C0851AV Dual-Port SramPackage Diagrams Ball Fbga 15 x 15 x 1.25 mmPin Thin Quad Flat Pack 24 × 24 × 1.4 mm Document History Submis Orig. Description of Change Sion DateSales, Solutions, and Legal Information Worldwide Sales and Design Support Products PSoC SolutionsUSB
Top Page Image Contents