Cypress CY7C0852AV, CY7C0850AV, CY7C0851AV manual CY7C0853AV

Page 4

CY7C0850AV, CY7C0851AV

CY7C0852AV, CY7C0853AV

Pin Configurations (continued)

Figure 2. 172-Ball BGA (Top View)

1

2

3

4

5

6

7

8

9

10

11

12

13

14

A

DQ32L

DQ30L

NC

VSS

DQ13L

VDD

DQ11L

DQ11R

VDD

DQ13R

VSS

NC

DQ30R

DQ32R

B

A0L

DQ33L

DQ29L

DQ17L

DQ14L

DQ12L

DQ9L

DQ9R

DQ12R

DQ14R

DQ17R

DQ29R

DQ33R

A0R

C

A17L

A1L

DQ31L

DQ27L

DQ15L

DQ10L

DQ10R

DQ15R

DQ27R

DQ31R

A1R

A17R

INTL

INTR

D

A2L

A3L

DQ35L

DQ34L

DQ28L

DQ16L

VSS

VSS

DQ16R

DQ28R

DQ34R

DQ35R

A3R

A2R

E

A4L

A5L

VDD

VDD

VSS

VDD

VDD

VDD

A5R

A4R

B0L

B0R

F

VDD

A6L

A7L

VDD

VSS

A7R

A6R

VDD

B1L

B1R

G

CY7C0853AV

VSS

VSS

OEL

B2L

B3L

B3R

B2R

OER

H

VSS

A8L

CLKL

CLKR

A8R

VSS

R/WL

R/WR

J

A9L

A10L

VSS

VSS

VSS

VDD

VSS

A10R

A9R

MRST

K

A11L

A12L

A15L

VDD

VDD

VDD

VSS

VDD

VDD

A15R

A12R

A11R

L

VDD

A13L

VSS

DQ26L

DQ25L

DQ19L

VSS

VSS

DQ19R

DQ25R

DQ26R

VSS

A13R

VDD

M

A16L

A14L

DQ22L

DQ18L

TDI

DQ7L

DQ2L

DQ2R

DQ7R

TCK

DQ18R

DQ22R

A14R

A16R

N

DQ24L

DQ20L

DQ8L

DQ6L

DQ5L

DQ3L

DQ0L

DQ0R

DQ3R

DQ5R

DQ6R

DQ8R

DQ20R

DQ24R

P

DQ23L

DQ21L

TDO

VSS

DQ4L

VDD

DQ1L

DQ1R

VDD

DQ4R

VSS

TMS

DQ21R

DQ23R

Document #: 38-06070 Rev. *H

Page 4 of 32

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Contents Functional Description Product Selection Guide Density Mbit 32K x 64K x 128K x176TQFP 172FBGA Cypress Semiconductor Corporation 198 Champion CourtLogic Block Diagram TrueRAM Array Mirror RegPin Configurations Ball BGA Top ViewCY7C0853AV CY7C0850AV CY7C0851AV CY7C0852AV Pin Definitions Mailbox Interrupts Master ResetOperation Description Address Counter and Mask Register Operations Mask Reset Operation Counter InterruptRetransmit Mask Load OperationCnten ADS Cntrst Mrst CLKProgrammable Counter-Mask Register Operation 1 Performing a TAP Reset Ieee 1149.1 Serial Boundary Scan JtagElectrical Characteristics Maximum RatingsOperating Range CapacitanceSwitching Characteristics Normal Load Load Three-state Delay LoadPort to Port Delays Master Reset TimingJtag Timing Parameter Description 167/133/100 Unit MinSwitching Waveforms Master ResetBank Select Read 26 Read-to-Write-to-Read OE Controlled 25, 28, 30 Write with Address Counter Advance Disabled-to-Write-to-Read-to-Write-to-Read Read-to-Readback-to-Read-to-Read R/W = High Counter Reset 32 Readback State of Address Counter or Mask Register35, 36, 37 LeftPort LPort Write to RightPort RPort Read39, 40 Counter Interrupt and Retransmit 34, 42, 43, 44 CLK Ordering Information 256K × 36 9M 3.3V Synchronous CY7C0853AV Dual-Port Sram128K × 36 4M 3.3V Synchronous CY7C0852AV Dual-Port Sram 64K × 36 2M 3.3V Synchronous CY7C0851AV Dual-Port SramPackage Diagrams Ball Fbga 15 x 15 x 1.25 mmPin Thin Quad Flat Pack 24 × 24 × 1.4 mm Document History Submis Orig. Description of Change Sion DateWorldwide Sales and Design Support Products PSoC Solutions Sales, Solutions, and Legal InformationUSB