Cypress CY7C0851AV, CY7C0852AV, CY7C0853AV, CY7C0850AV manual Clk

Page 27

CY7C0850AV, CY7C0851AV

CY7C0852AV, CY7C0853AV

Switching Waveforms (continued)

Figure 23. MailBox Interrupt Timing[46, 47, 48, 49, 50]

 

tCYC2

 

 

tCH2

tCL2

 

 

CLKL

 

 

 

 

tSA

tHA

 

L_PORT

3FFFF

An

ADDRESS

 

 

 

tSINT

An+1

An+2

An+3

INTR

tCYC2

tCH2 tCL2

CLKR

tSA tHA

tRINT

R_PORT

Am

ADDRESS

Am+1

 

 

3FFFF

 

 

Am+3

 

 

 

Am+4

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Table 7. Read/Write and Enable Operation (Any Port) [1, 8, 51, 52]

 

 

 

 

 

 

 

Inputs

 

 

Outputs

Operation

 

OE

 

CLK

 

CE0

CE1

R/W

DQ0 – DQ35

 

 

 

 

 

X

 

 

 

 

 

 

H

X

X

High-Z

Deselected

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

X

 

 

 

 

 

 

X

L

X

High-Z

Deselected

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

X

 

 

 

 

 

 

L

H

L

DIN

Write

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

L

 

 

 

 

 

 

L

H

H

DOUT

Read

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

H

 

 

X

 

L

H

X

High-Z

Outputs Disabled

 

 

 

 

 

 

 

 

 

 

 

 

 

Notes

46.CE0 = OE = ADS = CNTEN = LOW; CE1 = CNTRST = MRST = CNT/MSK = HIGH.

47.Address “3FFFF” is the mailbox location for R_Port of a 9M device.

48.L_Port is configured for Write operation, and R_Port is configured for Read operation.

49.At least one byte enable (B0 – B3) is required to be active during interrupt operations.

50.Interrupt flag is set with respect to the rising edge of the Write clock, and is reset with respect to the rising edge of the Read clock.

51.OE is an asynchronous input signal.

52.When CE changes state, deselection and Read happen after one cycle of latency.

Document #: 38-06070 Rev. *H

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Contents Cypress Semiconductor Corporation 198 Champion Court Functional DescriptionProduct Selection Guide Density Mbit 32K x 64K x 128K x 176TQFP 172FBGAMirror Reg Logic Block DiagramTrue RAM ArrayBall BGA Top View Pin ConfigurationsCY7C0853AV CY7C0850AV CY7C0851AV CY7C0852AV Pin Definitions Master Reset Mailbox InterruptsOperation Description Address Counter and Mask Register Operations Mask Load Operation Mask Reset OperationCounter Interrupt RetransmitCLK Cnten ADS Cntrst MrstProgrammable Counter-Mask Register Operation 1 Ieee 1149.1 Serial Boundary Scan Jtag Performing a TAP ResetCapacitance Electrical CharacteristicsMaximum Ratings Operating RangeNormal Load Load Three-state Delay Load Switching CharacteristicsMaster Reset Timing Port to Port DelaysParameter Description 167/133/100 Unit Min Jtag TimingMaster Reset Switching WaveformsBank Select Read 26 Read-to-Write-to-Read OE Controlled 25, 28, 30 Write with Address Counter Advance Disabled-to-Write-to-Read-to-Write-to-Read Read-to-Readback-to-Read-to-Read R/W = High Counter Reset 32 Readback State of Address Counter or Mask Register35, 36, 37 LeftPort LPort Write to RightPort RPort Read39, 40 Counter Interrupt and Retransmit 34, 42, 43, 44 CLK 64K × 36 2M 3.3V Synchronous CY7C0851AV Dual-Port Sram Ordering Information256K × 36 9M 3.3V Synchronous CY7C0853AV Dual-Port Sram 128K × 36 4M 3.3V Synchronous CY7C0852AV Dual-Port SramBall Fbga 15 x 15 x 1.25 mm Package DiagramsPin Thin Quad Flat Pack 24 × 24 × 1.4 mm Submis Orig. Description of Change Sion Date Document HistorySales, Solutions, and Legal Information Worldwide Sales and Design Support Products PSoC SolutionsUSB
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