Cypress CY7C0853AV, CY7C0852AV, CY7C0850AV manual Functional Description, 176TQFP 172FBGA

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CY7C0850AV, CY7C0851AV

CY7C0852AV, CY7C0853AV

FLEx36™ 3.3V 32K/64K/128K/256K x 36 Synchronous Dual-Port RAM

Features

True dual-ported memory cells that allow simultaneous access of the same memory location

Synchronous pipelined operation

Organization of 1-Mbit, 2-Mbit, 4-Mbit, and 9-Mbit devices

Pipelined output mode allows fast operation

0.18-micron CMOS for optimum speed and power

High-speed clock to data access

3.3V low power

Active as low as 225 mA (typ)

Standby as low as 55 mA (typ)

Mailbox function for message passing

Global master reset

Separate byte enables on both ports

Commercial and industrial temperature ranges

IEEE 1149.1-compatible JTAG boundary scan

172-Ball FBGA (1 mm pitch) (15 mm × 15 mm)

176-Pin TQFP (24 mm × 24 mm × 1.4 mm)

Counter wrap around control

Functional Description

The FLEx36™ family includes 1M, 2M, 4M, and 9M pipelined, synchronous, true dual-port static RAMs that are high-speed, low-power 3.3V CMOS. Two ports are provided, permitting independent, simultaneous access to any location in memory. The result of writing to the same location by more than one port at the same time is undefined. Registers on control, address, and data lines allow for minimal setup and hold time.

During a Read operation, data is registered for decreased cycle time. Each port contains a burst counter on the input address register. After externally loading the counter with the initial address, the counter increments the address internally (more details to follow). The internal Write pulse width is independent of the duration of the R/W input signal. The internal Write pulse is self-timed to allow the shortest possible cycle times.

A HIGH on CE0 or LOW on CE1 for one clock cycle powers down the internal circuitry to reduce the static power consumption. One cycle with chip enables asserted is required to reactivate the outputs.

Additional features include: readback of burst-counter internal address value on address lines, counter-mask registers to control the counter wrap-around, counter interrupt (CNTINT) flags, readback of mask register value on address lines, retransmit functionality, interrupt flags for message passing, JTAG for boundary scan, and asynchronous Master Reset (MRST).

Internal mask register controls counter wrap-around

Counter-interrupt flags to indicate wrap-around

Memory block retransmit operation

Counter readback on address lines

Mask register readback on address lines

Dual Chip Enables on both ports for easy depth expansion

The CY7C0853AV device in this family has limited features. Please see See “Address Counter and Mask Register Operations” on page 8. for details.

Table 1. Product Selection Guide

Density

1-Mbit

2-Mbit

4-Mbit

9-Mbit

(32K x 36)

(64K x 36)

(128K x 36)

(256K x 36)

 

Part Number

CY7C0850AV

CY7C0851AV

CY7C0852AV

CY7C0853AV

 

 

 

 

 

Max. Speed (MHz)

167

167

167

133

 

 

 

 

 

Max. Access Time - Clock to Data (ns)

4.0

4.0

4.0

4.7

 

 

 

 

 

Typical operating current (mA)

225

225

225

270

 

 

 

 

 

Package

176TQFP

176TQFP

176TQFP

172FBGA

 

172FBGA

172FBGA

172FBGA

 

Cypress Semiconductor Corporation • 198 Champion Court

San Jose, CA 95134-1709

408-943-2600

Document #: 38-06070 Rev. *H

 

 

Revised July 29, 2008

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Contents Product Selection Guide Density Mbit 32K x 64K x 128K x Functional Description176TQFP 172FBGA Cypress Semiconductor Corporation 198 Champion CourtTrue Logic Block DiagramRAM Array Mirror RegBall BGA Top View Pin ConfigurationsCY7C0853AV CY7C0850AV CY7C0851AV CY7C0852AV Pin Definitions Mailbox Interrupts Master ResetOperation Description Address Counter and Mask Register Operations Counter Interrupt Mask Reset OperationRetransmit Mask Load OperationCLK Cnten ADS Cntrst MrstProgrammable Counter-Mask Register Operation 1 Ieee 1149.1 Serial Boundary Scan Jtag Performing a TAP ResetMaximum Ratings Electrical CharacteristicsOperating Range CapacitanceNormal Load Load Three-state Delay Load Switching CharacteristicsMaster Reset Timing Port to Port DelaysParameter Description 167/133/100 Unit Min Jtag TimingMaster Reset Switching WaveformsBank Select Read 26 Read-to-Write-to-Read OE Controlled 25, 28, 30 Write with Address Counter Advance Disabled-to-Write-to-Read-to-Write-to-Read Read-to-Readback-to-Read-to-Read R/W = High Counter Reset 32 Readback State of Address Counter or Mask Register35, 36, 37 LeftPort LPort Write to RightPort RPort Read39, 40 Counter Interrupt and Retransmit 34, 42, 43, 44 CLK 256K × 36 9M 3.3V Synchronous CY7C0853AV Dual-Port Sram Ordering Information128K × 36 4M 3.3V Synchronous CY7C0852AV Dual-Port Sram 64K × 36 2M 3.3V Synchronous CY7C0851AV Dual-Port SramBall Fbga 15 x 15 x 1.25 mm Package DiagramsPin Thin Quad Flat Pack 24 × 24 × 1.4 mm Submis Orig. Description of Change Sion Date Document HistoryWorldwide Sales and Design Support Products PSoC Solutions Sales, Solutions, and Legal InformationUSB