Cypress CY7C0853AV manual Counter Interrupt, Retransmit, Mask Reset Operation, Mask Load Operation

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CY7C0850AV, CY7C0851AV CY7C0852AV, CY7C0853AV

Counter Interrupt

The counter interrupt (CNTINT) is asserted LOW when an increment operation results in the unmasked portion of the counter register being all “1s.” It is deasserted HIGH when an Increment operation results in any other value. It is also de-asserted by Counter Reset, Counter Load, Mask Reset and Mask Load operations, and by MRST.

Retransmit

Retransmit is a feature that allows the Read of a block of memory more than once without the need to reload the initial address. This eliminates the need for external logic to store and route data. It also reduces the complexity of the system design and saves board space. An internal “mirror register” is used to store the initially loaded address counter value. When the counter unmasked portion reaches its maximum value set by the mask register, it wraps back to the initial value stored in this “mirror register.” If the counter is continuously configured in increment mode, it increments again to its maximum value and wraps back to the value initially stored into the “mirror register.” Thus, the repeated access of the same data is allowed without the need for any external logic.

Mask Reset Operation

The mask register is reset to all “1s,” which unmasks every bit of the counter. Master reset (MRST) also resets the mask register to all “1s.”

Mask Load Operation

The mask register is loaded with the address value presented at the address lines. Not all values permit correct increment opera- tions. Permitted values are of the form 2n – 1 or 2n – 2. From the most significant bit to the least significant bit, permitted values have zero or more “0s,” one or more “1s,” or one “0.” Thus 1FFFF, 003FE, and 00001 are permitted values, but 1F0FF, 003FC, and 00000 are not.

Mask Readback Operation

The internal value of the mask register can be read out on the address lines. Readback is pipelined; the address is valid tCM2 after the next rising edge of the port’s clock. If mask readback occurs while the port is enabled (CE0 LOW and CE1 HIGH), the data lines (DQs) is three-stated. Figure 4 on page 10 shows a block diagram of the operation.

Counting by Two

When the least significant bit of the mask register is “0,” the counter increments by two. This may be used to connect the CY7C0850AV/CY7C0851AV/CY7C0852AV as a 72-bit single port SRAM in which the counter of one port counts even addresses and the counter of the other port counts odd addresses. This even-odd address scheme stores one half of the 72-bit data in even memory locations, and the other half in odd memory locations.

Document #: 38-06070 Rev. *H

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Contents Product Selection Guide Density Mbit 32K x 64K x 128K x Functional Description176TQFP 172FBGA Cypress Semiconductor Corporation 198 Champion CourtTrue Logic Block DiagramRAM Array Mirror RegBall BGA Top View Pin ConfigurationsCY7C0853AV CY7C0850AV CY7C0851AV CY7C0852AV Pin Definitions Master Reset Mailbox InterruptsOperation Description Address Counter and Mask Register Operations Counter Interrupt Mask Reset OperationRetransmit Mask Load OperationCLK Cnten ADS Cntrst MrstProgrammable Counter-Mask Register Operation 1 Ieee 1149.1 Serial Boundary Scan Jtag Performing a TAP ResetMaximum Ratings Electrical CharacteristicsOperating Range CapacitanceNormal Load Load Three-state Delay Load Switching CharacteristicsMaster Reset Timing Port to Port DelaysParameter Description 167/133/100 Unit Min Jtag TimingMaster Reset Switching WaveformsBank Select Read 26 Read-to-Write-to-Read OE Controlled 25, 28, 30 Write with Address Counter Advance Disabled-to-Write-to-Read-to-Write-to-Read Read-to-Readback-to-Read-to-Read R/W = High Counter Reset 32 Readback State of Address Counter or Mask Register35, 36, 37 LeftPort LPort Write to RightPort RPort Read39, 40 Counter Interrupt and Retransmit 34, 42, 43, 44 CLK 256K × 36 9M 3.3V Synchronous CY7C0853AV Dual-Port Sram Ordering Information128K × 36 4M 3.3V Synchronous CY7C0852AV Dual-Port Sram 64K × 36 2M 3.3V Synchronous CY7C0851AV Dual-Port SramBall Fbga 15 x 15 x 1.25 mm Package DiagramsPin Thin Quad Flat Pack 24 × 24 × 1.4 mm Submis Orig. Description of Change Sion Date Document HistorySales, Solutions, and Legal Information Worldwide Sales and Design Support Products PSoC SolutionsUSB
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