Cypress CY7C0850AV, CY7C0852AV, CY7C0853AV, CY7C0851AV manual Bank Select Read 26

						CY7C0850AV, CY7C0851AV
						CY7C0852AV, CY7C0853AV
Switching Waveforms (continued)
		Figure 10. Bank Select Read[26, 27]
	tCYC2
	tCH2	tCL2
CLK
	tSA	tHA
ADDRESS(B1)	A0	A	A		A3	A4		A5
		1		2
	tSC	tHC
CE(B1)
		tCD2	tSC	tHC	tCD2	tCKHZ	tCD2	tCKHZ
DATA			Q0		Q1			Q3
OUT(B1)		tHA
	t			t	t		t
	SA
				DC	DC		CKLZ
ADDRESS	A	A	A	2	A3	A4		A5
(B2)	0	1
			tSC		tHC
CE(B2)
	t	t				tCD2	tCKHZ	tCD2
DATAOUT(B2)	SC	HC
						Q		Q4
						2
					tCKLZ			tCKLZ
	Figure 11. Read-to-Write-to-Read (OE = LOW)[25, 28, 29, 30, 31]
	t	tCYC2t
	CH2	CL2
CLK
CE
	tSC	tHC

	tSW	tHW
R/W
tSW	tHW
An	An+1	An+2	An+2	An+3		An+4
ADDRESS			tSD tHD
tSA	tHA
DATAIN	t	t	Dn+2	tCD2		tCD2
	CD2	CKHZ
DATAOUT	Qn			tCKLZ	Qn+1	Qn+3
	READ	NO OPERATION		WRITE	READ

Notes

26.In this depth-expansion example, B1 represents Bank #1 and B2 is Bank #2; each bank consists of one Cypress CY7C0851AV/CY7C0852AV device from this data sheet. ADDRESS(B1) = ADDRESS(B2).

27.ADS = CNTEN= B0 – B3 = OE = LOW; MRST = CNTRST = CNT/MSK = HIGH.

28.Output state (HIGH, LOW, or high-impedance) is determined by the previous cycle control signals.

29.During “No Operation,” data in memory at the selected address may be corrupted and should be rewritten to ensure data integrity.

30.CE0 = OE = B0 – B3 = LOW; CE1 = R/W = CNTRST = MRST = HIGH.

31.CE0 = B0 – B3 = R/W = LOW; CE1 = CNTRST = MRST = CNT/MSK = HIGH. When R/W first switches low, since OE = LOW, the Write operation cannot be completed (labelled as no operation). One clock cycle is required to three-state the I/O for the Write operation on the next rising edge of CLK.

Document #: 38-06070 Rev. *H Page 18 of 32

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