Cypress CY7C0852AV, CY7C0853AV, CY7C0850AV Jtag Timing, Parameter Description 167/133/100 Unit Min

Page 16

CY7C0850AV, CY7C0851AV

CY7C0852AV, CY7C0853AV

JTAG Timing

	Parameter	Description	167/133/100		Unit
	Parameter	Description	Min	Max	Unit
			Min	Max
	fJTAG	Maximum JTAG TAP Controller Frequency		10	MHz
	tTCYC	TCK Clock Cycle Time	100		ns
	tTH	TCK Clock HIGH Time	40		ns
	tTL	TCK Clock LOW Time	40		ns
	tTMSS	TMS Setup to TCK Clock Rise	10		ns
	tTMSH	TMS Hold After TCK Clock Rise	10		ns
	tTDIS	TDI Setup to TCK Clock Rise	10		ns
	tTDIH	TDI Hold After TCK Clock Rise	10		ns
	tTDOV	TCK Clock LOW to TDO Valid		30	ns
	tTDOX	TCK Clock LOW to TDO Invalid	0		ns

Figure 7. JTAG Switching Waveform

Test Clock

TCK

Test Mode Select

TMS

Test Data-In

TDI

tTH

tTMSS

tTDIS

tTL

tTCYC

tTMSH

tTDIH

Test Data-Out

TDO

tTDOX

tTDOV

Document #: 38-06070 Rev. *H

Page 16 of 32

[+] Feedback

Image 16

Contents Functional Description Product Selection Guide Density Mbit 32K x 64K x 128K x176TQFP 172FBGA Cypress Semiconductor Corporation 198 Champion CourtLogic Block Diagram TrueRAM Array Mirror RegPin Configurations Ball BGA Top ViewCY7C0853AV CY7C0850AV CY7C0851AV CY7C0852AV Pin Definitions Mailbox Interrupts Master ResetOperation Description Address Counter and Mask Register Operations Mask Reset Operation Counter InterruptRetransmit Mask Load OperationCnten ADS Cntrst Mrst CLKProgrammable Counter-Mask Register Operation 1 Performing a TAP Reset Ieee 1149.1 Serial Boundary Scan JtagElectrical Characteristics Maximum RatingsOperating Range CapacitanceSwitching Characteristics Normal Load Load Three-state Delay LoadPort to Port Delays Master Reset TimingJtag Timing Parameter Description 167/133/100 Unit MinSwitching Waveforms Master ResetBank Select Read 26 Read-to-Write-to-Read OE Controlled 25, 28, 30 Write with Address Counter Advance Disabled-to-Write-to-Read-to-Write-to-Read Read-to-Readback-to-Read-to-Read R/W = High Counter Reset 32 Readback State of Address Counter or Mask Register35, 36, 37 LeftPort LPort Write to RightPort RPort Read39, 40 Counter Interrupt and Retransmit 34, 42, 43, 44 CLK Ordering Information 256K × 36 9M 3.3V Synchronous CY7C0853AV Dual-Port Sram128K × 36 4M 3.3V Synchronous CY7C0852AV Dual-Port Sram 64K × 36 2M 3.3V Synchronous CY7C0851AV Dual-Port SramPackage Diagrams Ball Fbga 15 x 15 x 1.25 mmPin Thin Quad Flat Pack 24 × 24 × 1.4 mm Document History Submis Orig. Description of Change Sion DateWorldwide Sales and Design Support Products PSoC Solutions Sales, Solutions, and Legal InformationUSB