Cypress CY7C0850AV, CY7C0852AV, CY7C0853AV, CY7C0851AV Read-to-Readback-to-Read-to-Read R/W = High

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CY7C0850AV, CY7C0851AV

 

 

 

 

 

CY7C0852AV, CY7C0853AV

Switching Waveforms (continued)

 

 

 

 

 

 

 

 

 

 

Figure 18. Read-to-Readback-to-Read-to-Read (R/W = HIGH)

 

 

 

 

 

 

tCYC2

 

 

 

 

 

 

 

 

 

tCL2

tCH2

 

 

 

 

 

 

 

 

CLK

 

 

 

 

 

 

 

 

 

 

 

tSAD

tHAD

 

 

 

 

 

 

 

 

ADS

 

 

 

 

 

 

 

 

 

 

CNTEN

 

 

 

 

 

 

 

 

 

 

 

tSCN tHCN

 

 

tSA

tHA

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ADDRESS

 

 

 

 

 

An+1

 

 

 

 

COUNTER

An

 

An+1

 

An+2

 

 

 

 

 

INTERNAL

 

 

 

An+3

 

An+4

 

ADDRESS

 

 

 

 

 

 

 

 

 

 

OE

 

 

 

 

 

 

 

 

 

 

DATAOUT

 

 

 

Q

 

 

 

Qn+2

Q

n+3

 

 

 

 

n+1

 

 

 

 

 

 

READ

NO OPERATION

READ

 

READ

 

READ

 

INCREMENT

READBACK

INCREMENT

INCREMENT

 

INCREMENT

 

Document #: 38-06070 Rev. *H

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Contents 176TQFP 172FBGA Functional DescriptionProduct Selection Guide Density Mbit 32K x 64K x 128K x Cypress Semiconductor Corporation 198 Champion CourtRAM Array Logic Block DiagramTrue Mirror RegPin Configurations Ball BGA Top ViewCY7C0853AV CY7C0850AV CY7C0851AV CY7C0852AV Pin Definitions Mailbox Interrupts Master ResetOperation Description Address Counter and Mask Register Operations Retransmit Mask Reset OperationCounter Interrupt Mask Load OperationCnten ADS Cntrst Mrst CLKProgrammable Counter-Mask Register Operation 1 Performing a TAP Reset Ieee 1149.1 Serial Boundary Scan JtagOperating Range Electrical CharacteristicsMaximum Ratings CapacitanceSwitching Characteristics Normal Load Load Three-state Delay LoadPort to Port Delays Master Reset TimingJtag Timing Parameter Description 167/133/100 Unit MinSwitching Waveforms Master ResetBank Select Read 26 Read-to-Write-to-Read OE Controlled 25, 28, 30 Write with Address Counter Advance Disabled-to-Write-to-Read-to-Write-to-Read Read-to-Readback-to-Read-to-Read R/W = High Counter Reset 32 Readback State of Address Counter or Mask Register35, 36, 37 LeftPort LPort Write to RightPort RPort Read39, 40 Counter Interrupt and Retransmit 34, 42, 43, 44 CLK 128K × 36 4M 3.3V Synchronous CY7C0852AV Dual-Port Sram Ordering Information256K × 36 9M 3.3V Synchronous CY7C0853AV Dual-Port Sram 64K × 36 2M 3.3V Synchronous CY7C0851AV Dual-Port SramPackage Diagrams Ball Fbga 15 x 15 x 1.25 mmPin Thin Quad Flat Pack 24 × 24 × 1.4 mm Document History Submis Orig. Description of Change Sion DateWorldwide Sales and Design Support Products PSoC Solutions Sales, Solutions, and Legal InformationUSB