Cypress CY7C0853AV Maximum Ratings, Operating Range, Electrical Characteristics, Capacitance

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CY7C0850AV, CY7C0851AV CY7C0852AV, CY7C0853AV

Maximum Ratings

Exceeding maximum ratings[15] may impair the useful life of the device. These user guidelines are not tested.

Storage Temperature

–65°C to + 150°C

Ambient Temperature...........................................with

–55°C to + 125°C

Power Applied

Supply Voltage to Ground Potential

–0.5V to + 4.6V

DC Voltage Applied to

 

Outputs in High-Z State

–0.5V to VDD + 0.5V

DC Input Voltage

–0.5V to VDD + 0.5V[16]

Output Current into Outputs (LOW)

20 mA

Static Discharge Voltage

> 2000V

(JEDEC JESD22-A114-2000B)

 

Latch-up Current

 

> 200 mA

Operating Range

 

 

 

 

Range

Ambient Temperature

VDD

Commercial

0°C to +70°C

3.3V ± 165 mV

 

 

 

Industrial

–40°C to +85°C

3.3V ± 165 mV

 

 

 

Electrical Characteristics

Over the Operating Range

Parameter

Description

 

 

 

 

 

-167

 

 

-133

 

 

-100

 

Unit

 

 

 

 

 

Min

Typ.

Max

Min

Typ.

Max

Min

Typ.

Max

VOH

Output HIGH Voltage (VDD = Min., IOH= –4.0 mA)

2.4

 

 

2.4

 

 

2.4

 

 

V

VOL

Output LOW Voltage (VDD = Min., IOL= +4.0 mA)

 

 

0.4

 

 

0.4

 

 

0.4

V

VIH

Input HIGH Voltage

 

 

 

 

 

2.0

 

 

2.0

 

 

2.0

 

 

V

VIL

Input LOW Voltage

 

 

 

 

 

 

 

0.8

 

 

0.8

 

 

0.8

V

IOZ

Output Leakage Current

 

 

 

 

 

–10

 

10

–10

 

10

–10

 

10

μA

IIX1

Input Leakage Current Except TDI, TMS,

MRST

 

–10

 

10

–10

 

10

–10

 

10

μA

IIX2

Input Leakage Current TDI, TMS,

MRST

 

–0.1

 

1.0

–0.1

 

1.0

–0.1

 

1.0

mA

ICC

Operating Current for

 

CY7C0850AV

 

225

300

 

225

300

 

 

 

mA

 

(VDD = Max.,IOUT = 0 mA),

 

CY7C0851AV

 

 

 

 

 

 

 

 

 

 

 

Outputs Disabled

 

CY7C0852AV

 

 

 

 

 

 

 

 

 

 

 

 

 

CY7C0853AV

 

 

 

 

270

400

 

200

310

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ISB1[18]

Standby Current (Both Ports TTL Level)

 

90

115

 

90

115

 

90

115

mA

 

CEL and CER VIH, f = fMAX

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ISB2[18]

Standby Current (One Port TTL Level)

 

160

210

 

160

210

 

160

210

mA

 

CEL CER VIH, f = fMAX

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ISB3[18]

Standby Current (Both Ports CMOS Level)

 

55

75

 

55

75

 

55

75

mA

 

CEL and CER VDD – 0.2V, f = 0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ISB4[18]

Standby Current (One Port CMOS Level)

 

160

210

 

160

210

 

160

210

mA

 

CEL CER VIH, f = fMAX

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ISB5

Operating Current

 

CY7C0853AV

 

 

 

 

70

100

 

70

100

mA

 

(VDD = Max, IOUT = 0 mA, f = 0)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Outputs Disabled

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Capacitance

Part Number[17]

Parameter

Description

Test Conditions

Max

Unit

CY7C0850AV,

CIN

Input Capacitance

TA = 25°C, f = 1 MHz,

13

pF

CY7C0851AV, CY7C0852AV

 

 

VDD = 3.3V

 

 

COUT

Output Capacitance

10

pF

CY7C0853AV

CIN

Input Capacitance

 

22

pF

 

COUT

Output Capacitance

 

20

pF

Notes

15.The voltage on any input or I/O pin can not exceed the power pin during power up.

16.Pulse width < 20 ns.

17.COUT also references CI/O.

18.ISB1, ISB2, ISB3 and ISB4 are not applicable for CY7C0853AV because it can not be powered down by using chip enable pins.

Document #: 38-06070 Rev. *H

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Contents Product Selection Guide Density Mbit 32K x 64K x 128K x Functional Description176TQFP 172FBGA Cypress Semiconductor Corporation 198 Champion CourtTrue Logic Block DiagramRAM Array Mirror RegBall BGA Top View Pin ConfigurationsCY7C0853AV CY7C0850AV CY7C0851AV CY7C0852AV Pin Definitions Mailbox Interrupts Master ResetOperation Description Address Counter and Mask Register Operations Counter Interrupt Mask Reset OperationRetransmit Mask Load OperationCLK Cnten ADS Cntrst MrstProgrammable Counter-Mask Register Operation 1 Ieee 1149.1 Serial Boundary Scan Jtag Performing a TAP ResetMaximum Ratings Electrical CharacteristicsOperating Range CapacitanceNormal Load Load Three-state Delay Load Switching CharacteristicsMaster Reset Timing Port to Port DelaysParameter Description 167/133/100 Unit Min Jtag TimingMaster Reset Switching WaveformsBank Select Read 26 Read-to-Write-to-Read OE Controlled 25, 28, 30 Write with Address Counter Advance Disabled-to-Write-to-Read-to-Write-to-Read Read-to-Readback-to-Read-to-Read R/W = High Counter Reset 32 Readback State of Address Counter or Mask Register35, 36, 37 LeftPort LPort Write to RightPort RPort Read39, 40 Counter Interrupt and Retransmit 34, 42, 43, 44 CLK 256K × 36 9M 3.3V Synchronous CY7C0853AV Dual-Port Sram Ordering Information128K × 36 4M 3.3V Synchronous CY7C0852AV Dual-Port Sram 64K × 36 2M 3.3V Synchronous CY7C0851AV Dual-Port SramBall Fbga 15 x 15 x 1.25 mm Package DiagramsPin Thin Quad Flat Pack 24 × 24 × 1.4 mm Submis Orig. Description of Change Sion Date Document HistoryWorldwide Sales and Design Support Products PSoC Solutions Sales, Solutions, and Legal InformationUSB